APL5934 datasheet(16/24 Pages) ANPEC

16 / 24 page

Rev. A.1 - Mar., 2016

www.anpec.com.tw

APL5934

Layout Consideration

Figure 2

Thermal Consideration

Please solder the Exposed Pad on the ground pad

on the top-layer of PCBs. The ground pad must have

wide size to conduct heat into the ambient air through

the ground plane and PCB as a heat sink.

Please place the input capacitors for VIN and VCNTL

pins near the pins as close as possible for

decoupling high-frequency ripples.

Ceramic decoupling capacitors for load must be

placed near the load as close as possible for

decoupling high-frequency ripples.

To place APL5934 and output capacitors near the

load reduces parasitic resistance and inductance

for excellent load transient response.

The negative pins of the input and output capacitors

and the GND pin must be connected to the ground

plane of the load.

Large current paths, shown by bold lines on the fig-

ure 1, must have wide tracks.

Place the R1, R2, and C1 near the APL5934 as close

as possible to avoid noise coupling.

Connect the ground of the R2 to the GND pin by us-

ing a dedicated track.

Connect the one pin of the R1 to the load for Kelvin

sensing.

10. Connect one pin of the C1 to the VOUT pin for reli-

able feedback compensation.

Refer to the figure 2, the SOP-8P is a cost-effective pack-

age featuring a small size like a standard SOP-8 and a

bottom exposed pad to minimize the thermal resistance

of the package, being applicable to high current applica-

tions. The exposed pad must be soldered to the top-layer

VIN plane. The copper of the VIN plane on the Top layer

conducts heat into the PCB and ambient air. Please en-

large the area of the top-layer pad and the VIN plane to

reduce the case-to-ambient resistance (

CA).

Recommended Minimum Footprint

0.050

0.024

0.138

Unit : Inch

SOP-8P

Exposed Pad

Die

Top ground

plane

PCB

Ambient

Air

118 mil

102 mil

SOP-8P

Top VOUT plane

VCNTL

VOUT

CCNTL

VIN

GND

VOUT

VCNTL

VIN

CIN

COUT

APL5934

Load

Figure 1

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