TLF12325

September 1995

CGS2536V

Commercial Quad 1 to 4 Clock Drivers

CGS2536TV

Industrial Quad 1 to 4 Clock Drivers

General Description

These Clock Generation and Support clock drivers are spe-

cifically designed for driving memory arrays requiring large

fanouts while operating at high speeds

This device meets the rise and fall time requirements of the

The CGS2536 IO structures are CMOS The outputs are

separated into two banks of eight One bank consists of

divide by two outputs the other straight-through buffers

Within each bank half the outputs are inverting the other

half non-inverting

The CGS2536 specification guarantees part-to-part skew

variation

Features

Y

Guaranteed

10 ns rise and fall times while driving 12 inches of

50X microstrip terminated with 25 pF

Y

650 ps part-to-part variation on positive or negative

transition

Y

Operates with either 33V or 50V supply

Y

Y

Y

Y

Symmetric package orientation

Y

Large fanout for memory driving applications

Y

Guaranteed 2 kV ESD protection

Y

Implemented on National’s ABT family process

Y

28-pin PLCC for optimum skew performance

Connection Diagrams

Pin Assignment for 28-Pin PLCC

TLF12325 – 1

Truth Table

Input

Output

In 0

In 1

In 2

ABCD Out (2)

In 3

ABCD Out (3)

CGS2536

TLF12325 – 2

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A