Data Sheet

ADM1270

Rev. A | Page 15 of 21

THEORY OF OPERATION

When circuit boards are inserted into a live backplane, discharged

supply bypass capacitors draw large transient currents from the

backplane power bus as they charge. These transient currents

can cause permanent damage to connector pins, as well as voltage

dips on the backplane supply that can reset other boards in the

system.

The ADM1270 is designed to control the inrush current when

powering on the system, allowing a board to be inserted safely

into a live backplane by protecting it from excess currents.

The ADM1270 is a current-limiting controller that provides

inrush current limiting and overcurrent protection for modular

or battery-powered systems. The voltage developed across a

sense resistor in the power path is measured with a current

sense amplifier via the VCC/SENSE+ and SENSE− pins. A

default limit of 50 mV is set, but this limit can be adjusted, if

required, using a resistor divider network from the VCAP pin

to the ISET pin.

The ADM1270 limits the current through the sense resistor by

controlling the gate voltage of an external P-channel FET in the

power path, via the GATE pin. The sense voltage and, therefore,

the load current is maintained below the preset maximum. The

ADM1270 protects the external FET by limiting the time that

the FET remains on while the current is at its maximum value.

This current-limit time is set by the choice of capacitors

connected to the TIMER pin and the TIMER_OFF pin. This

current-limit time helps to maintain the FET in its SOA.

In addition to the timer function, there is a foldback pin (FLB)

that is used to provide additional FET protection. The current

limit is linearly reduced by the voltage on the FLB pin, so that

current limit used by the device is lower, again helping to ensure

the FET is kept within its SOA.

A minimum voltage clamp ensures that even if the FLB voltage

is 0 V, the current is never reduced to zero, which otherwise

prevents the device from powering up.

The ADM1270 features OV and UV protection, programmed

using external resistor dividers on the UV and OV pins.

A PWRGD signal can be used to indicate when the output

supply is greater than a voltage programmed using an external

resistor divider on the FB_PG pin.

To protect the system from a reverse polarity input supply, there

is a provision made to control an additional external P-channel

FET with the RPFG pin. This feature allows for a low on-resistance,

low voltage drop FET to be used in place of a diode to perform

the same function, thus saving power losses and improving overall

efficiency. The reverse voltage protection FET prevents negative

input voltages that can damage the load or the ADM1270.

1V

1V

GATE DRIVE/

LOGIC

TIMER

ON

TIMEOUT

CURRENT

LIMIT

TIMER

VCC/SENSE+ SENSE–

GATE

TIMER

GND

UV

OV

RPFG

FLB

LDO

VCAP

REF

SELECT

ISET

FAULT

FB_PG

ENABLE

TIMER_OFF

PWRGD

+

+

+

–

–

+

–

–

CURRENT-

LIMIT

CONTROL

ADM1270

Figure 34. Simplified Functional Block Diagram