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ADP3205

Multiphase IMVP-IV

Core Controller for Mobile CPUs

FEATURES

Pin Programmable 1-, 2-, or 3-Phase Operation

Excellent Static and Dynamic Current Sharing

Superior Load Transient Response when Used with

ADOPT™ Optimal Positioning Technology

Noise-Blanking for Speed and Stability

Synchronous Rectification Control for Optimized Light

Load Efficiency

Soft DAC Output Voltage Transition for VID Change

Cycle-by-Cycle Current Limiting

Latched or Hiccup Current Overload Protection

Masked Power Good during Output Voltage Transients

Soft Start-Up without Power-On In-Rush Current Surge

2-Level Overvoltage and Reverse-Voltage Protection

APPLICATIONS

IMVP-IV CPU Core DC-to-DC Converters

Programmable Output Power Supplies

GENERAL DESCRIPTION

The ADP3205 is a 1-, 2-, or 3-phase hysteretic peak current mode

dc-to-dc buck converter controller dedicated to powering a mobile

processor’s core. The chip optimized low voltage design runs from

the 3.3 V system supply. The chip contains a precision 6-bit DAC

whose nominal output voltage is set by VID code. The ADP3205

features high speed operation to allow a minimized inductor size

that results in the fastest possible change of current to the output.

To further minimize the number of output capacitors, the con-

verter features active voltage positioning enhanced with ADOPT

optimal compensation to ensure a superior load transient response.

The output signals interface with ADP3415 MOSFET drivers,

which that are optimized for high speed and high efficiency. The

ADP3205 is capable of providing synchronous rectification control

to extend battery lifetime in light load conditions.

The ADP3205 is specified over the extended commercial temperature

range of 0

°C to 100°C and is available in a 40-lead LFCSP package.

FUNCTIONAL BLOCK DIAGRAM

CORE

CMP

VID0

VID1

VID2

VID3

VID4

DACREF

GND

VCC

REG

ADP3205

SS

COREFB

PWRGD

SD

DPRSLP

HYSSET

DPSHIFT

CLAMP

RAMP

CS1

CS2

DPSLP

HYSTERESIS SET

AND

CLIM SET

CS+

DPRSET

VID5

BOOTSET

CURRENT

SENSE

MUX

CS–

CLIM/ZCS

CMP

HYS/CLIM

CONTROL

AND

CS MUX/

PHASE CONTROL

DRVCTRL

DRV2

DRV1

DRVLSD2

DRVLSD1

DAC

RES

NETWORK

REF

MUX

MASK

OVP

LATCH

RVP

LATCH

VRV

VOV

UVLO CMP

BIAS ENABLER

ALARM RST

SS/LATCH-OFF

TIMER

BAND GAP

AND

REF AMP

RVP CMP

ALARM

LATCHEN

VREF

VBG

RST

COREGD

PWRGD

LATCH

EOFSS

BOOT

19

DVP CMP

VDACREF

VBG

BOOT

CORE ABOVE CMP

CORE BELOW CMP

DRVCTRL

35

TSYNC

PSI

DRV3

40

DRVLSD3

VREF

PRWGD

MASKING

PRWGD

DELAY

DPWRGD

TPWRGD

CLKEN

22

DACREF

FB

34

CS3

33

36

37

VBG

DPSHIFT

SET

VREF

VREF

VBG

38

39