PARAMETERS

CONDITIONS

UNITS

FREQUENCY DOMAIN RESPONSE

-3dB bandwidth

V

30

90

MHz

35

MHz

gain flatness

flatness

DC to 30MHz

3

0.3

dB

peaking

DC to 200MHz

0

0

dB

rolloff

DC to 60MHz

1.5

dB

TIME DOMAIN RESPONSE

rise and fall time

0.5V step

13.9

4.7

ns

2.0V step

13.5

ns

overshoot

0.5V step

0

0

%

slew rate

0.5V step

35

200

V/

µs

DISTORTION AND NOISE RESPONSE

0.5V

-32

dBc

-37

dBc

-29

dBc

1.0V

-43

dBc

STATIC DC PERFORMANCE

small-signal gain

AC-coupled

0.89

0.94

V/V

supply current

∞

0.75

1.6

mA

MISCELLANEOUS PERFORMANCE

output voltage range

R

∞

1.5

2.8

V

pp

Ω

1.1

2.6

Ω

Ω

Ω

Ω

Ω, unless noted)

Operation

The CLC109 is a low-power, high-speed unity-gain buffer.

It uses a closed-loop topology which allows for accuracy

not usually found in high-speed buffers. A closed-loop

design provides high accuracy and low output impedance

through a wide bandwidth.

Single Supply Operation

Although the CLC109 is specified to operate from split

±5V power supplies, there is no internal ground reference

that prevents operation from a single voltage power

supply. For single supply operation the input signal should

be biased at a DC value of ½V

can be

accomplished by AC coupling and rebiasing as shown in

the "Typical Application" illustrations on the front page.

The above electrical specifications provide typical

performance specifications for the CLC109 at 25°C while

operating from a single +3V or a single +5V power supply.

Printed Circuit Layout and Supply Bypassing

As with any high-frequency device, a good PCB layout is

required for optimum performance.

This is especially

important for a device as fast as the CLC109.

To minimize capacitive feedthrough, pins 2, 3, 6, and 7

should be connected to the ground plane, as shown in

Figure 1. Input and output traces should be laid out as

transmission lines with the appropriate termination resistors

very near the CLC109.

On a 0.065 inch epoxy PCB

material, a 50

Ωtransmissionline(commonlycalledstripline)

can be constructed by using a trace width of 0.1" over a

complete ground plane.

Figure 1 shows recommended power supply bypassing.

Parasitic or load capacitance directly on the output of the

CLC109 will introduce additional phase shift in the device.

This phase shift can decrease phase margin and increase

frequency response peaking.

A small series resistor

inserted between pin 6 and the capacitance effectively

decouples this effect. The graphs on the following page

illustrate the required resistor value and the resulting

performance vs. capacitance.

Precision buffed resistors (PRP8351 series from Precision

Resistive Products), which have low parasitic reactances,

were used to develop the data sheet specifications.

Precision carbon composition resistors or standard spirally-

trimmed RN55D metal film resistors will work, though they

may cause a slight degradation of ac performance due to

their reactive nature at high frequencies.

Evaluation Boards

Evaluation boards are available from National as part

CLC730012 (DIP) and CLC730045 (SOIC). This board

was used in the characterization of the device and provides

optimal performance. Designers are encouraged to copy

these printed circuit board layouts for their applications.

Figure 1: Recommended circuit & evaluation

board schematic

C4

C3

C2

C1

+5V

-5V

0.01

µF

0.01

µF

6.8

µF

6.8

µF

+

+

5

4

2

3

6

7

8

1

CLC109

desired output impedance.

for desired

input impedance.

3

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