TAS3004 datasheet(21/80 Pages) TI

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2.3.3

MSB Left-Justified Serial Interface Format—Monaural ADC Mode, B Left Input Selected

The monaural output mode for the MSB left-justified serial interface format is for 16, 18, 20, and 24 bits with the

following bits in the analog control register set as shown:

•

Bit 7 (ADM) is set to 1.

•

Bit 6 (LRB) is cleared to 0.

•

Bit 1 (INP) is set to 1.

Figure 2–6 shows the following characteristics of this protocol:

•

Left channel is transmitted when LRCLK is either high or low.

•

The SDIN data is justified to the leading edge of the LRCLK.

•

The MSBs are transmitted at the same time as LRCLK edge and captured at the next rising edge of SCLK.

SCLK

LRCLK = fS

MSB

LSB

…… MSB

LSB

……

SDIN

MSB

LSB

…… MSB

LSB

……

Left Channel

SDOUT0

……

Figure 2–6. MSB Left-Justified Serial Interface Format—Monaural ADC Mode, B Left Input Selected

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