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39SF020 数据表(PDF) 13 Page - Silicon Storage Technology, Inc |
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39SF020 数据表(HTML) 13 Page - Silicon Storage Technology, Inc |
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13 / 23 page ![]() 13 © 1998 Silicon Storage Technology, Inc. 326-10 12/98 2 Megabit Multi-Purpose Flash SST39SF020 Preliminary Specifications 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FIGURE 10: SOFTWARE ID ENTRY AND READ 326 ILL F09.3 ADDRESS A14-0 TIDA DQ7-0 WE# SW0 SW1 SW2 5555 2AAA 5555 0000 0001 OE# CE# Three-byte sequence for Software ID Entry TWP TWPH TAA BF B6 55 AA 90 FIGURE 9: WE# CONTROLLED CHIP ERASE TIMING DIAGRAM Note: The device also supports CE# controlled chip erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 10) 326 ILL F17.1 ADDRESS A17-0 DQ7-0 WE# SW0 SW1 SW2 SW3 SW4 SW5 5555 2AAA 2AAA 5555 5555 55 10 55 AA 80 AA 5555 OE# CE# SIX-BYTE CODE FOR CHIP ERASE TSCE TWP |
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