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RTC-8564JE 数据表(PDF) 2 Page - List of Unclassifed Manufacturers

部件名 RTC-8564JE
功能描述  I2C-BUS INTERFACE REAL TIME CLOCK MODULE
PDF  2 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
网页  
标志 ETC - List of Unclassifed Manufacturers

RTC-8564JE 数据表(HTML) 2 Page - List of Unclassifed Manufacturers

  RTC-8564JE Datasheet HTML 1Page - List of Unclassifed Manufacturers RTC-8564JE Datasheet HTML 2Page - List of Unclassifed Manufacturers  
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70
Real time clock module
Switching characteristics
Block diagram
Register table
Timing chart
INT
SCL
SDA
CLKOUT
32.768 kHz
CRYSTAL
OSC
POR
Output
Control
Divider
Voltage
Detector
Control
Logic
Address
Register
Timer
Timer Control
CLKOUT frequency
Weekday Alarm
Day Alarm
Hour Alarm
Minutes Alarm
Years
Month/Century
Weekdays
Days
Hours
Minutes
Seconds
Control2
Control1
00
0F
I C-BUS
Interface
2
Protocol
Start
Condition (s)
Stop
Condition (P)
tSU;STO
tHD;DAT
tHD;STA
tSU;STA
tLOW tHIGH
1/fSCL
tr
tf
tBUF
tSU;DAT
Bit 7
MSB (A7)
Bit6
(A6)
Bit0
LSB
(R/W)
ACK
(A)
SCL
SDA
CLKOE
0 : Always set this bit to“0”.
Address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Register symbol
Control 1
Control 2
Sec
Min
Hour
Day
Week
Month/Century
Year
Minutes Alarm
Hours Alarm
Day Alarm
Week Alarm
CLKOUT frequency
Timer control
Timer
bit 7
TEST
0
VL
∗
∗
∗
∗
C
Year 80
AE
AE
AE
AE
FE
TE
128
bit 6
0
0
S 40
Min 40
∗
∗
∗
∗
Year 40
A-Min 40
A-Hr 40
∗
∗
∗
∗
64
bit 5
STOP
0
S 20
Min 20
Hour 20
Day 20
∗
∗
Year 20
A-Min 20
A-Hr 20
A-Day 20
∗
∗
∗
32
bit 4
0
TI/TP
S 10
Min 10
Hour 10
Day 10
∗
Month 10
Year 10
A-Min 10
A-Hr 10
A-Day 10
∗
∗
∗
16
bit 3
TEST
AF
S 8
Min 8
Hour 8
Day 8
∗
Month 8
Year 8
A-Min 8
A-Hr 8
A-Day 8
∗
∗
∗
8
bit 2
0
TF
S 4
Min 4
Hour 4
Day 4
W 4
Month 4
Year 4
A-Min 4
A-Hr 4
A-Day 4
A-W 4
∗
∗
4
bit 1
0
AIE
S 2
Min 2
Hour 2
Day 2
W 2
Month 2
Year 2
A-Min 2
A-Hr 2
A-Day 2
A-W 2
FD1
TD1
2
bit 0
0
TIE
S 1
Min 1
Hour 1
Day 1
W 1
Month 1
Year 1
A-Min 1
A-Hr 1
A-Day 1
A-W 1
FD0
TD0
1
Item
SCL clock frequency
Tolerance spike time on bus
Start condition set-up time
Start condition Hold time
SCL “L” time
SCL “H” time
SCL and SDA rise time
SCL and SDA fall time
Date set-up time
Date hold time
Stop condition set-up time
Symbol
fSCL
tSW
tSU;STA
tHD;STA
tLOW
tHIGH
tr
tf
tSU;DAT
tHD;DAT
tSU;STO
Min.
0.6
1.3
0.6
100
0
4.0
Max.
400
50
0.3
Unit
kHz
ns
µs
ns
µs
(VDD=1.8 to 5.5 V, Ta=-40 ˚C to +85 ˚C)



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