5

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DC Gain (unity gain buffer)

is left open. Parasitic capacitance at the inverting node

frequency response.

DC Gain (inverting)

The inverting DC voltage gain for the configuration

shown in Figure 2 is

.

Figure 2: Inverting Gain

The normalized gain plots in the

Typical Performance

Characteristics

section

show

different

feedback

recommended for obtaining the highest bandwidth with

non-inverting input.

≥ 5, the minimum recommended R

.

At large

See the

AC Design (small signal bandwidth)

sub-section for the tradeoffs.

DC Gain (transimpedance)

Figure 3 shows a transimpedance circuit where the cur-

The DC transimpedance gain is:

maintain a flat frequency response.

Figure 3: Transimpedance Gain

DC Design (level shifting)

Figure 4 shows a DC level shifting circuit for inverting

shift of

, which is independent of the DC

Figure 4: Level Shifting Circuit

DC Design (single supply)

a voltage divider that sets the non-inverting input DC volt-

age. This circuit has a DC gain of 1. A low

itor

previous stage. Both capacitors make a high pass

Figure 5: Single Supply Circuit

The complete gain equation for the circuit in Figure 5 is:

A

R

R

v

f

g

=−

+

-

CLC446

0.1

µF

6.8

µF

0.1

µF

6.8

µF

3

2

4

7

6

+

+

R

R

A

g

f

v

=

A

V

I

R

R

o

in

f

== −

+

-

CLC446

0.1

µF

6.8

µF

0.1

µF

6.8

µF

3

2

4

7

6

+

+

+

-

CLC446

+

-

CLC446

V

V

s

1s

1s

1

R

R

1s

o

in

1

1

2

f

g

2

=

+

⋅

+⋅ +













+

τ

τ

τ

τ

−⋅

V

R

R

ref

f

ref