CLC449 datasheet(5/12 Pages) NSC

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Figure 2: Inverting Gain

The normalized gain plots in the

Typical Performance

Characteristics section show different feedback resistors,

Rf, for different gains. These values of Rf are recommended

for obtaining the highest bandwidth with minimal peaking.

The resistor Rt in Figure 2 provides DC bias for the non-

inverting input.

For |Av|

≤ 4, calculate the recommended R

f as follows:

≅ 295 - |A

v| • Ri, where Ri = 45Ω. For |Av| > 4, the

minimum recommended feedback resistor is Rf = 100 Ω.

Select Rg to set the DC gain:

At large gains, Rg becomes small and will load the

previous stage.

This situation is resolved by driving

Rg with a low impedance buffer like the CLC111,

or increasing Rf and Rg (see the Bandwidth (Small

Signal) sub-section for the tradeoffs).

Accurate DC gain is usually limited by the tolerance of

the external resistors Rf and Rg.

Bandwidth (Small Signal)

The CLC449 current-feedback amplifier bandwidth is a

function of the feedback resistor (Rf), not of the DC volt-

age gain (Av).

The bandwidth is approximately

proportional to 1/Rf. As a rule, if Rf doubles, the band-

width is cut in half. Other AC specifications will also be

degraded.

Decreasing Rf from the recommended

value increases peaking and for very small values of

Rf oscillation will occur.

With an inverting amplifier design, peaking is sometimes

observed. This is often the result of layout parasitics

caused by inadequate ground planes or long traces. If

this is observed, placing a 50 to 200

Ω resistor between

the non-inverting pin and ground will usually reduce the

peaking.

Bandwidth (Minimum Slew Rate)

Slew rate influences the bandwidth for large signal

sinusoids. To determine an approximate value of slew

rate, necessary to support large sinusoids use the

following equation:

≅ 5 • f • V

peak

Vpeak is the peak output sinusoidal voltage, f is the

frequency of the sinusoid.

The slew rate of the CLC449 in inverting gains is always

higher than in non-inverting gains.

DC Design (Level Shifting)

Figure 3 shows a DC level shifting circuit for inverting

gain configurations. Vref produces a DC output level shift

which is independent of the DC output produced by Vin.

Figure 3: Level Shifting Circuit

DC Design (Single Supply)

Figure 4 is a typical single-supply circuit. Resistors R1

and R2 form a voltage divider that sets the non-inverting

input DC voltage. This circuit has a DC gain of 1. The

coupling capacitor C1 isolates the DC bias point from the

previous stage.

Both capacitors make a high pass

response; the high frequency gain is determined by Rf

and Rg.

Figure 4: Single Supply Circuit

The complete gain equation for the circuit in Figure 4 is:

where s = j

ω, τ

1 = (R1|| R2)

•

C1, and τ2 = RgC2.

DC Design (DC Offsets)

The DC offset model shown in Figure 5 is used to

calculate the output offset voltage. The equation for out-

put offset voltage is:

The current offset terms, IBN and IBI, do not track each

other. The specifications are stated in terms of

magnitude only. Therefore, the terms Vos, IBN, and IBI

may have either positive or negative polarity. Matching

the equivalent resistance seen at both input pins does

not reduce the output offset voltage.

CLC449

0.1

µF

6.8

µF

Vin

Vcc

0.1

µF

6.8

µF

Vee

|A |

-V

ref

⋅

Vin

Req2

CLC449

Vref

Rref

Req1

CLC449

Vin

Vcc

oos

eq1

eq2

=−

⋅

()⋅+











 +⋅

()

⋅

+⋅ +













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