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LS7220 数据表(PDF) 3 Page - LSI Computer Systems |
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LS7220 数据表(HTML) 3 Page - LSI Computer Systems |
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3 / 4 page ![]() SENSE Input I1 I2 LOCK LOCK STATUS SAVE Input SAVE STATUS LOCK Input FIGURE 3. LS7220 TIMING DIAGRAM TPW T PW TPW TPW TCE TSE TSE TSE TSE TSD T SD I3 I4 6 5 4 3 2 13 12 UNSELECTED KEYS (RESET) SEQUENTIAL DETECTOR INCORRECT SEQUENCE CORRECT SEQUENCE SEQUENTIAL MEMORY POWER ON RESET SAVE MEMORY LOGIC "1" LEVEL RESTORE LOCK LOCK STATUS 8 10 SAVE STATUS CONVENIENCE DELAY - + V SS C SELECTED KEYS (IN SEQUENCE) I 1 I 2 I3 I4 1 14 9 V SS V DD (+V) (-V) V SS V SS V SS V SS V DD 11 7 R S Q R S Q Q SAVE INPUT LOCK INPUT Capacitor Discharge Current FIGURE 4. LS7220 BLOCK DIAGRAM SENSE INPUT (ENABLE) R External Capacitor FIGURE 2. CONVENIENCE DELAY TIME vs POWER SUPPLY (with External Capacitor C, Pin 12) Typical Curve for C = 5µF TA = 25 °C (V SS-V DD), Volts 5 10 15 18 8 4 6 2 14 0 12 10 7220-012703-3 |
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