PIC16F877ATISLASHP datasheet(82/234 Pages) MICROCHIP

82 / 234 page

PIC16F87XA

DS39582B-page 80

 2003 Microchip Technology Inc.

9.4

I2C Mode

The MSSP module in I2C mode fully implements all

master and slave functions (including general call sup-

port) and provides interrupts on Start and Stop bits in

hardware to determine a free bus (multi-master func-

tion). The MSSP module implements the standard

mode specifications, as well as 7-bit and 10-bit

addressing.

Two pins are used for data transfer:

• Serial clock (SCL) – RC3/SCK/SCL

• Serial data (SDA) – RC4/SDI/SDA

The user must configure these pins as inputs or outputs

through the TRISC<4:3> bits.

FIGURE 9-7:

MSSP BLOCK DIAGRAM

(I2C MODE)

9.4.1

REGISTERS

The MSSP module has six registers for I2C operation.

These are:

• MSSP Control Register (SSPCON)

• MSSP Control Register 2 (SSPCON2)

• MSSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer Register

(SSPBUF)

• MSSP Shift Register (SSPSR) – Not directly

accessible

• MSSP Address Register (SSPADD)

SSPCON, SSPCON2 and SSPSTAT are the control

and status registers in I2C mode operation. The

SSPCON and SSPCON2 registers are readable and

writable. The lower six bits of the SSPSTAT are

read-only. The upper two bits of the SSPSTAT are

read/write.

SSPSR is the shift register used for shifting data in or

out. SSPBUF is the buffer register to which data bytes

are written to or read from.

SSPADD register holds the slave device address

when the SSP is configured in I2C Slave mode. When

the SSP is configured in Master mode, the lower

seven bits of SSPADD act as the baud rate generator

reload value.

In receive operations, SSPSR and SSPBUF together

create a double-buffered receiver. When SSPSR

receives a complete byte, it is transferred to SSPBUF

and the SSPIF interrupt is set.

During transmission, the SSPBUF is not double-

buffered. A write to SSPBUF will write to both SSPBUF

and SSPSR.

Read

Write

SSPSR reg

Match Detect

SSPADD reg

Start and

Stop bit Detect

SSPBUF reg

Internal

Data Bus

Addr Match

Set, Reset

S, P bits

(SSPSTAT reg)

RC3/SCK/SCL

RC4/SDI/

Shift

Clock

MSb

LSb

SDA

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