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CLC5633IM 数据表(PDF) 13 Page - National Semiconductor (TI) |
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CLC5633IM 数据表(HTML) 13 Page - National Semiconductor (TI) |
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13 / 17 page ![]() Application Division (Continued) The input is AC coupled to prevent the need for level shifting the input signal at the source. The resistive voltage divider biases the non-inverting input to V CC ÷ 2 = 2.5V (For VCC = +5V). Dual Supply Operation The CLC5633 operates on dual supplies as well as signal supplies. The non-inverting and inverting configurations are shown in Figure 7, Figure 8, and Figure 9. Load Termination The CLC5633 can source and sink near equal amounts of current. For optimum performance, the load should be tied to V CM. CLC5633 0.1 µF 6.8 µF + VCC Note: Channel 2 and 3 not shown. 1 14 2 13 3 12 4 11 5 10 6 9 7 8 1k Ω 1k Ω + - 1k Ω 1k Ω + - 1k Ω 1k Ω V V 2.5 Low frequency cutoff 1 2R C o in g C =− + = π where Rg = 1kΩ. , Vin R R VCC CC Vo DS015005-42 FIGURE 4. AC Coupled, A V = −1V/V Configuration CLC5633 0.1 µF 6.8 µF + VCC Note: Channel 2 and 3 not shown. 1 14 2 13 3 12 4 11 5 10 6 9 7 8 1k Ω 1k Ω + - 1k Ω 1k Ω + - 1k Ω 1k Ω Vo Vin R R VCC CC V 2V 2.5 Low frequency cutoff 1 2R C where R R 2 RR o in in C in source =+ = =>> π , C DS015005-43 FIGURE 5. AC Coupled, A V = +1V/V Configuration CLC5633 0.1 µF 6.8 µF + VCC Note: Channel 2 and 3 not shown. 1 14 2 13 3 12 4 11 5 10 6 9 7 8 1k Ω 1k Ω + - 1k Ω 1k Ω + - 1k Ω 1k Ω Vo Vin R R VCC CC V 2V 2.5 Low frequency cutoff 1 2R C where R R 2 RR o in in C in source =+ = =>> π , C DS015005-44 FIGURE 6. AC Coupled, A V = +2V/V Configuration CLC5633 0.1 µF 6.8 µF + VCC 1 14 2 13 3 12 4 11 5 10 6 9 7 8 1k Ω 1k Ω + - 1k Ω 1k Ω + - 1k Ω 1k Ω Vo Vin Rt Note: Rb provides DC bias for the non-inverting input. Select Rt to yield desired Rin = Rt||1kΩ. Channel 2 and 3 not shown. Rb 6.8 µF 0.1 µF + VEE DS015005-45 FIGURE 7. Dual Supply, A V = −1V/V Configuration CLC5633 0.1 µF 6.8 µF + VCC 1 14 2 13 3 12 4 11 5 10 6 9 7 8 1k Ω 1k Ω + - 1k Ω 1k Ω + - 1k Ω 1k Ω Vo Vin Rt Note: Channel 2 and 3 not shown. 6.8 µF 0.1 µF + VEE DS015005-46 FIGURE 8. Dual Supply, A V = +1V/V Configuration CLC5633 0.1 µF 6.8 µF + VCC 1 14 2 13 3 12 4 11 5 10 6 9 7 8 1k Ω 1k Ω + - 1k Ω 1k Ω + - 1k Ω 1k Ω Vo Vin Rt Note: Channel 2 and 3 not shown. 6.8 µF 0.1 µF + VEE DS015005-47 FIGURE 9. Dual Supply, A V= + 2V/V Configuration www.national.com 13 |
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