ZR36060PQC datasheet(17/46 Pages) ETC

17 / 46 page

Integrated JPEG CODEC

The ADDR[1:0] address pins map 4 direct access registers

(Figure 16 and Figure 17):

To access the ZR36060’s internal Code FIFO (in Code Slave

mode only), read and write operations are directed to address

00b. For more information on the Code FIFO access, please

refer to section 5.0 “Code Interface”.

To access the ZR36060’s internal registers and markers array,

the host must first write the 10-bit host address, followed by a

read or write to the 8-bit host data register. Note that the host

address is not self-incrementing. However, it does not need to be

re-written every data access, only if a different register or

memory location is to be accessed. The host address of the

location to be accessed can be changed by writing the LSB reg-

ister, the MSB register, or both, as required.

The host interface is an asynchronous interface (see Figure 18).

Internally, however, all the interface I/O is synchronized to an

internal clock (at twice the VCLKx2 frequency), so VCLKx2 must

exist and be stable before any host access can take place.

A Host-ZR36060 handshake is performed using the WR or RD

strobe pulses, and the ACK signal. Some time after WR or RD

goes low, ACK is activated by the ZR36060 to acknowledge that

it is ready to input or output host or code data. Only after this

event, the host is allowed to release the strobe. The ZR36060

acknowledges the end of access by releasing the ACK signal.

A slow host may extend the strobe pulse beyond the activation

of the ACK signal by the ZR36060. In a read cycle, data from the

ZR36060 stays on the bus until after the RD signal is deasserted.

In a write cycle, the data is strobed in on the rising edge of WR.

Note that, if it is guaranteed that the minimum WR or RD strobe

width is always larger than the minimum specified in the AC

Characteristics, the ACK signal can be ignored.

When accessing the Code FIFO (address 00b) in Code Slave

mode, the ACK signal reflects also the CBUSY status (see

section 5.0 “Code Interface” for more details). (But CBUSY is

only used by the host in Code Slave mode and must be ignored

in all other host accesses.)

For a complete description of the internal memory register

mapping, please refer to section 8.0 “Register and Memory

Description”.

4.1 Interrupt Request and Associated Registers

The ZR36060 is capable of requesting an interrupt from the host

controller through its JIRQ output signal. This section describes

the protocol and registers involved the interrupt request.

An interrupt request can occur due to one or more of the follow-

ing events:

• Assertion of the DATERR output (a data corruption event).

• Assertion of the END output.

• Assertion of the EOI (end-of-image marker detection) output

during decompression.

• End of the active rectangle of the video field (EOAV) which is

being processed by the ZR36060.

Each one of the events has a dedicated bit (DATERR, END, EOI,

and EOAV, respectively) in the Interrupt Mask Register that

enables or disables it as an interrupt requesting event.

Each of the events also has a status bit in the Interrupt Status

The DATERR bit, and the END bit exactly reflect the level of the

DATERR and END output pins, respectively, but with positive

logic (as opposed to the negative logic of the output pins).

Figure 16. Address Space of ZR36060 in Code Master Mode

MSB

Host Address LSB

Host Data

ADDR[1:0]

DATA[7:0]

R/W

Host Address

(10 Bits)

Figure 17. Address Space of ZR36060 in Code Slave Mode

MSB

Host Address LSB

Host Data

ADDR[1:0]

DATA[7:0]

R/W

Host Address

(10 Bits)

CODE FIFO

CODE[7:0]*

CODE FIFO

R/W

The Code FIFO register can be 8 or 16 bits wide, depending on the Code16 parameter.

When in 16-bit Code Slave mode, the CODE[7:0] bus is an extension of the DATA]7:0] bus.

(*)

Figure 18. Asynchronous Operation of the Host Interface

DATA[7:0]

ADDR[1:0]

Read Operation

ACK

Host Address

Host Data

DATA[7:0]

ADDR[1:0]

Write Operation

ACK

Host Address

Host Data

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