COP688CL datasheet(21/40 Pages) NSC

21 / 40 page

Multi-Input Wakeup (Continued)

be individually enabled or disabled The register WKEDG

specifies the trigger condition to be either a positive or a

negative edge Finally the register WKPND latches in the

pending trigger conditions

The GIE (Global Interrupt Enable) bit enables the interrupt

function

A control flag LPEN functions as a global interrupt enable

for Port L interrupts Setting the LPEN flag will enable inter-

rupts and vice versa A separate global pending flag is not

needed since the register WKPND is adequate

Since Port L is also used for waking the device out of the

HALT or IDLE modes the user can elect to exit the HALT or

IDLE modes either with or without the interrupt enabled If

he elects to disable the interrupt then the device will restart

execution from the instruction immediately following the in-

struction that placed the microcontroller in the HALT or

IDLE modes In the other case the device will first execute

the interrupt service routine and then revert to normal oper-

ation

The Wakeup signal will not start the chip running immediate-

ly since crystal oscillators or ceramic resonators have a fi-

nite start up time The IDLE Timer (T0) generates a fixed

delay to ensure that the oscillator has indeed stabilized be-

fore allowing the device to execute instructions In this case

upon detecting a valid Wakeup signal only the oscillator

circuitry and the IDLE Timer T0 are enabled The IDLE Tim-

er is loaded with a value of 256 and is clocked from the tc

instruction cycle clock The tc clock is derived by dividing

down the oscillator clock by a factor of 10 A Schmitt trigger

following the CKI on-chip inverter ensures that the IDLE tim-

er is clocked only when the oscillator has a sufficiently large

amplitude to meet the Schmitt trigger specifications This

Schmitt trigger is not part of the oscillator closed loop The

startup timeout from the IDLE timer enables the clock sig-

nals to be routed to the rest of the chip If the RC clock

option is used the fixed delay is under software control A

control flag CLKDLY in the G7 configuration bit allows the

clock start up delay to be optionally inserted

Setting

CLKDLY flag high will cause clock start up delay to be in-

serted and resetting it will exclude the clock start up delay

The CLKDLY flag is cleared during reset so the clock start

up delay is not present following reset with the RC clock

options

Interrupts

The device supports a vectored interrupt scheme It sup-

ports a total of ten interrupt sources The following table

lists all the possible interrupt sources their arbitration rank-

ing and the memory locations reserved for the interrupt vec-

tor for each source

Two bytes of program memory space are reserved for each

interrupt source All interrupt sources except the software

interrupt are maskable Each of the maskable interrupts

have an Enable bit and a Pending bit A maskable interrupt

is active if its associated enable and pending bits are set If

GIE e 1 and an interrupt is active then the processor will

be interrupted as soon as it is ready to start executing an

instruction except if the above conditions happen during the

Software Trap service routine This exception is described

in the Software Trap sub-section

The interruption process is accomplished with the INTR in-

struction (opcode 00) which is jammed inside the Instruc-

Arbitration

Vector

Ranking

Source

Description

Address

Hi-Low Byte

(1) Highest

Software

INTR Instruction

0yFE – 0yFF

Reserved

for Future Use

0yFC – 0yFD

(2)

External

Pin G0 Edge

0yFA – 0yFB

(3)

Timer T0

Underflow

0yF8 – 0yF9

(4)

Timer T1

T1AUnderflow

0yF6 – 0yF7

(5)

Timer T1

T1B

0yF4 – 0yF5

(6)

MICROWIREPLUS

BUSY Goes Low

0yF2 – 0yF3

Reserved

for Future Use

0yF0 – 0yF1

Reserved

for UART

0yEE – 0yEF

Reserved

for UART

0yEC – 0yED

(7)

Timer T2

T2AUnderflow

0yEA – 0yEB

(8)

Timer T2

T2B

0yE8 – 0yE9

Reserved

for Future Use

0yE6 – 0yE7

Reserved

for Future Use

0yE4 – 0yE5

(9)

Port LWakeup

Port L Edge

0yE2 – 0yE3

(10) Lowest

Default

VIS Instr Execution

0yE0 – 0yE1

without Any Interrupts

y is VIS page y i 0

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