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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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AD1836AS 数据表(PDF) 3 Page - Analog Devices |
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AD1836AS 数据表(HTML) 3 Page - Analog Devices |
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3 / 18 page  PRELIMINARY TECHNICAL DATA REV. PrC –3– AD1836 DIGITAL FILTERS at 44.1 kHz Min Typ Max Unit ADC DECIMATION FILTER Pass Band 20 kHz Pass Band Ripple ±0.0001 dB Transition Band 22 kHz Stop Band 24 kHz Stop Band Attenuation 120 dB Group Delay TBD µs DAC INTERPOLATION FILTER Pass Band 20 kHz Pass Band Ripple ±0.01 dB Transition Band 22 kHz Stop Band 24 kHz Stop Band Attenuation 70 dB Group Delay TBD µs TIMING Parameter Min Max Unit Comments MASTER CLOCK AND RESET tMH MCLK High min max ns 256 × fS 512 × f S 768 × fS tML MCLK Low min max ns tMCLK MCLK Period min max ns fMCLK MCLK Freq min max ns tPDR PD/RST Low 4500 MCLK Periods Reset to SPI Register Write SPI PORT tCCH CCLK High min ns tCCL CCLK Low min ns tCCP CCLK Period min ns tCDS CDATA Setup min ns To CCLK Rising tCDH CDATA Hold min ns From CCLK Rising tCLS CLATCH Setup min ns To CCLK Rising tCLH CLATCH Hold min ns From CCLK Falling tCODE COUT Enable max ns From CCLK Falling tCOD COUT Delay max ns From CCLK Falling tCOH COUT Hold min ns From CCLK Falling tCOTS COUT Three-State max ns From CCLK Falling DAC SERIAL PORT Normal Modes tDBH DBCLK High min ns tDBL DBCLK Low min ns tDBP DBCLK Period min ns fDB DBCLK Freq max ns tDLS DLRCLK Setup min ns To DBCLK Rising tDLH DLRCLK Hold min ns From DBCLK Rising tDDS DSDATA Setup min ns To DBCLK Rising tDDH DSDATA Hold min ns From DBCLK Rising Packed 128, 256 Modes tDBH DBCLK High min ns tDBL DBCLK Low min ns tDBP DBCLK Period min ns fDB DBCLK Freq max ns tDLS DLRCLK Setup min ns To DBCLK Rising tDLH DLRCLK Hold min ns From DBCLK Rising tDDS DSDATA Setup min ns To DBCLK Rising tDDH DSDATA Hold min ns From DBCLK Rising |
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