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September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
13
Figure 1: Block Diagram
Array of Analog PSoC Blocks
SRAM
Memory
I/O Ports
Global I/O
Programmable Interconnect
Array of Digital PSoC Blocks
Analog Input
Muxing
D
B
A
0
0
A
C
A
0
0
D
B
A
0
3
D
B
A
0
2
D
B
A
0
1
D
C
A
0
4
D
C
A
0
7
D
C
A
0
6
D
C
A
0
5
Analog Output
Drivers
Comparator
Outputs
Clocks to
Analog
A
S
A
1
0
A
S
B
2
0
A
C
A
0
1
A
S
B
1
1
A
S
A
2
1
A
C
A
0
2
A
S
A
1
2
A
S
B
2
2
A
C
A
0
3
A
S
B
1
3
A
S
A
2
3
Internal System Bus
M8C CPU
Core
Flash Program
Memory
MAC
Multiply
Accumulate
Decimator
Watchdog/
Sleep Timer
LVD/POR
Interrupt
Controller
Oscillator
and PLL
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