COP888GD datasheet(20/42 Pages) NSC

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Multi-Input Wakeup (Continued)

selects the trigger condition to be a positive edge. Changing

an edge select entails several steps in order to avoid a

pseudo Wakeup condition as a result of the edge change.

First, the associated WKEN bit should be reset, followed by

the edge select change in WKEDG. Next, the associated

WKPND bit should be cleared, followed by the associated

WKEN bit being re-enabled.

An example may serve to clarify this procedure. Suppose we

wish to change the edge select from positive (low going high)

to negative (high going low) for L Port bit 5, where bit 5 has

previously been enabled for an input interrupt. The program

would be as follows:

RBIT

5, WKEN

; Disable MIWU

SBIT

5, WKEDG

; Change edge polarity

RBIT

5, WKPND

; Reset pending flag

SBIT

5, WKEN

; Enable MIWU

If the L port bits have been used as outputs and then

changed to inputs with Multi-Input Wakeup/Interrupt, a safety

procedure should also be followed to avoid inherited pseudo

wakeup conditions. After the selected L port bits have been

changed from output to input but before the associated

WKEN bits are enabled, the associated edge select bits in

WKEDG should be set or reset for the desired edge selects,

followed by the associated WKPND bits being cleared.

This same procedure should be used following reset, since

the L port inputs are left floating as a result of reset.

The occurrence of the selected trigger condition for

Multi-Input Wakeup is latched into a pending register called

WKPND. The respective bits of the WKPND register will be

set on the occurrence of the selected trigger edge on the cor-

responding Port L pin. The user has the responsibility of

clearing these pending flags. Since WKPND is a pending

the device will not enter the HALT mode if any Wakeup bit is

both enabled and pending. Consequently, the user has the

responsibility of clearing the pending flags before attempting

to enter the HALT mode.

WKEN, WKPND and WKEDG are all read/write registers,

and are cleared at reset.

PORT L INTERRUPTS

Port L provides the user with an additional eight fully select-

able, edge sensitive interrupts which are all vectored into the

same service subroutine.

The interrupt from Port L shares logic with the wake up cir-

cuitry. The register WKEN allows interrupts from Port L to be

individually enabled or disabled. The register WKEDG speci-

fies the trigger condition to be either a positive or a negative

edge. Finally, the register WKPND latches in the pending

trigger conditions.

The GIE (Global Interrupt Enable) bit enables the interrupt

function.

A control flag, LPEN, functions as a global interrupt enable

for Port L interrupts. Setting the LPEN flag will enable inter-

rupts and vice versa. A separate global pending flag is not

needed since the register WKPND is adequate.

Since Port L is also used for waking the device out of the

HALT or IDLE modes, the user can elect to exit the HALT or

IDLE modes either with or without the interrupt enabled. If he

elects to disable the interrupt, then the device will restart ex-

ecution from the instruction immediately following the in-

struction that placed the microcontroller in the HALT or IDLE

modes. In the other case, the device will first execute the in-

terrupt service routine and then revert to normal operation.

(See HALT MODE for clock option wakeup information.)

A/D Converter

The device contains an 8-channel, multiplexed input, suc-

cessive approximation, Analog-to Digital converter. The de-

vice’s VCC and GND pins are used for voltage reference.

OPERATING MODES

The A/D converter supports ratiometric measurements. It

supports both Single Ended and Differential modes of opera-

tion.

Four specific analog channel selection modes are sup-

ported. These are as follows:

Allow any specific channel to be selected at one time. The

A/D converter performs the specific conversion requested

and stops.

Allow any specific channel to be scanned continuously. In

other words, the user specifies the channel and the A/D con-

verter scans it continuously. At any arbitrary time the user

can immediately read the result of the last conversion. The

user must wait for only the first conversion to complete.

Allow any differential channel pair to be selected at one time.

The A/D converter performs the specific differential conver-

sion requested and stops.

Allow any differential channel pair to be scanned continu-

ously. In other words, the user specifies the differential chan-

nel pair and the A/D converter scans it continuously. At any

arbitrary time the user can immediately read the result of the

last differential conversion. The user must wait for only the

first conversion to complete.

The A/D converter is supported by two memory mapped reg-

isters, the result register and the mode control register.

When the device is reset, the mode control register (ENAD)

is cleared, the A/D is powered down and the A/D result reg-

ister has unknown data.

A/D Control Register

The ENAD control register contains 3 bits for channel selec-

tion, 2 bits for prescaler selection, 2 bits for mode selection

and a Busy bit. An A/D conversion is initiated by setting the

ADBSY bit in the ENAD control register. The result of the

conversion is available to the user in the A/D result register,

ADRSLT, when ADBSY is cleared by the hardware on

completion of the conversion.

ENAD (Address 0xCB)

CHANNEL

MODE

PRESCALER

BUSY

SELECT

ADCH2

ADCH1

ADCH0

ADMOD1

ADMOD0

PSC1

PSC0

ADBSY

Bit 7

Bit 0

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