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MPC875EC 数据表(PDF) 51 Page - Freescale Semiconductor, Inc |
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MPC875EC 数据表(HTML) 51 Page - Freescale Semiconductor, Inc |
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51 / 84 page  MPC875/MPC870 Hardware Specifications, Rev. 3.0 51 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics 74 L1CLKB edge to L1RSYNCB, L1TSYNCB, invalid (SYNC hold time) 35.00 — ns 75 L1RSYNCB, L1TSYNCB rise/fall time — 15.00 ns 76 L1RXDB valid to L1CLKB edge (L1RXDB setup time) 17.00 — ns 77 L1CLKB edge to L1RXDB invalid (L1RXDB hold time) 13.00 — ns 78 L1CLKB edge to L1ST1 and L1ST2 valid 4 10.00 45.00 ns 78A L1SYNCB valid to L1ST1 and L1ST2 valid 10.00 45.00 ns 79 L1CLKB edge to L1ST1 and L1ST2 invalid 10.00 45.00 ns 80 L1CLKB edge to L1TXDB valid 10.00 55.00 ns 80A L1TSYNCB valid to L1TXDB valid 4 10.00 55.00 ns 81 L1CLKB edge to L1TXDB high impedance 0.00 42.00 ns 82 L1RCLKB, L1TCLKB frequency (DSC =1) — 16.00 or SYNCCLK /2 MHz 83 L1RCLKB, L1TCLKB width low (DSC =1) P + 10 — ns 83a L1RCLKB, L1TCLKB width high (DSC = 1)3 P + 10 — ns 84 L1CLKB edge to L1CLKOB valid (DSC = 1) — 30.00 ns 85 L1RQB valid before falling edge of L1TSYNCB4 1.00 — L1TCLK 86 L1GRB setup time2 42.00 — ns 87 L1GRB hold time 42.00 — ns 88 L1CLKB edge to L1SYNCB valid (FSD = 00) CNT = 0000, BYT = 0, DSC = 0) —0.00 ns 1 The ratio SyncCLK/L1RCLKB must be greater than 2.5/1. 2 These specs are valid for IDL mode only. 3 Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns. 4 These strobes and TxD on the first bit of the frame become valid after the L1CLKB edge or L1SYNCB, whichever comes later. Table 21. SI Timing (continued) Num Characteristic All Frequencies Unit Min Max |
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