MB9B360R datasheet(2/166 Pages) CYPRESS

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Document Number: 002-04872 Rev.*A

Page 2 of 166

MB9B360R Series

[USB host]

USB2.0 Full/Low-speed supported

Bulk-transfer, interrupt-transfer and Isochronous-transfer

support

USB Device connected/dis-connected automatically detect

IN/OUT token handshake packet automatically

Max 256-byte packet-length supported

Wake-up function supported

Multi-function Serial Interface (Max 8 channels)

64 bytes with FIFO (the FIFO step numbers are variable

depending on the settings of the communication mode or bit

length.)

Operation mode is selectable from the followings for each

channel.



UART



CSIO



LIN



[UART]

Full-duplex double buffer

Selection with or without parity supported

Built-in dedicated baud rate generator

External clock available as a serial clock

Hardware Flow control : Automatically control the

transmission by CTS/RTS (only ch.4)

Various error detect functions available (parity errors, framing

errors, and overrun errors)

[CSIO]

Full-duplex double buffer

Built-in dedicated baud rate generator

Overrun error detect function available

Serial chip select function (ch.6 and ch.7 only)

Supports high-speed SPI (ch.4 and ch.6 only)

Data length 5 to 16-bit

[LIN]

LIN protocol Rev.2.1 supported

Full-duplex double buffer

Master/Slave mode supported

LIN break field generation (can change to 13 to 16-bit length)

LIN break delimiter generation (can change to 1 to 4-bit

length)

Various error detect functions available (parity errors, framing

errors, and overrun errors)

2C]

Standard mode (Max 100 kbps) / High-speed mode (Max

400 kbps) supported

Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.3=ch.A

and ch.7=ch.B) supported

DMA Controller (8 channels)

DMA Controller has an independent bus for CPU, so CPU and

DMA Controller can process simultaneously.

8 independently configured and operated channels

Transfer can be started by software or request from the

built-in peripherals

Transfer address area: 32-bit (4 Gbytes)

Transfer mode: Block transfer/Burst transfer/Demand

transfer

Transfer data type: bytes/half-word/word

Transfer block count: 1 to 16

Number of transfers: 1 to 65536

DSTC (Descriptor System data Transfer Controller)

(128 channels)

The DSTC can transfer data at high-speed without going via

the CPU. The DSTC adopts the Descriptor system and,

following the specified contents of the Descriptor which has

already been constructed on the memory, can access directly

the memory /peripheral device and performs the data transfer

operation.

It supports the software activation, the hardware activation and

the chain activation functions.

A/D Converter (Max 24 channels)

[12-bit A/D Converter]

Successive Approximation type

Built-in 3 units

Conversion time: 0.5μs @ 5V

Priority conversion available (priority at 2levels)

Scanning conversion mode

Built-in FIFO for conversion data storage (for SCAN

conversion: 16steps, for Priority conversion: 4steps)

DA converter (Max 2 channels)

R-2R type

12-bit resolution

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