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10

PCM1721

MAPPING OF PROGRAM REGISTERS

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

MODE0

res

res

res

res

res

A1

A0

LDL

AL7

AL6

AL5

AL4

AL3

AL2

AL1

AL0

MODE1

res

res

res

res

res

A1

A0

LDR

AR7

AR6

AR5

AR4

AR3

AR2

AR1

AR0

MODE2

res

res

res

res

res

A1

A0

PL3

PL2

PL1

PL0

IW1

IW0

OPE

DEM

MUT

MODE3

res

res

res

res

res

A1

A0

IZD

SF1

SF0

DSR1

DSR0

SYS

ATC

LRP

ATTENUATION DATA LOAD CONTROL, LCH

Bit 8 (LDL) is used to simultaneously set analog outputs of

Lch and Rch. An output level is controlled by AL[0:7]

attenuation data when this bit is set to 1. When set to 0, an

output level is not controlled and remains at the previous

attenuation level. A LDR bit in Register 1 has an equivalent

function as the LDL. When one of LDL or LDR is set to 1,

the output level of the left and right channel is simulta-

neously controlled. The attenuation level is given by:

ATT = 20 log (y/256) (dB), where y = x, when

0 ≤ x ≤ 254

y = x + 1, when x = 255

X is the user-determined step number, an integer value

between 0 and 255.

Example:

let x = 255

let x = 254

let x = 1

let x = 0

REGISTER 1 (A1 = 0, A0 = 1)

B15 B14 B13 B12 B11 B10 B9 B8

B7 B6

B5 B4 B3

B2 B1

B0

res res res res res

A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0

Register 1 is used to control right channel attenuation. As

in Register 1, bits 0 - 7 (AR0 - AR7) control the level of

attenuation.

PROGRAM REGISTER BIT MAPPING

PCM1721’s special functions are controlled using four pro-

gram registers which are 16 bits long. These registers are all

loaded using MD. After the 16 data bits are clocked in, ML

is used to latch in the data to the appropriate register. Table

IV shows the complete mapping of the four registers and

Figure 7 illustrates the serial interface timing.

ATT

= 20 log

255

+1

256







 =

0dB

ATT

= 20 log

254

256







 =

–0. 068dB

ATT

= 20 log

1

256







 =

– 48.16dB

ATT

= 20 log

0

256







 =

–

∞

REGISTER

BIT

NAME

NAME

DESCRIPTION

Register 0

AL (7:0)

DAC Attenuation Data for Lch

LDL

Attenuation Data Load Control for Lch

A (1:0)

Register Address

Res

Reserved

Register 1

AR (7:0)

DAC Attentuation Data for Rch

LDL

Attenuation Data Load Control for Rch

A (1:0)

Register Address

Res

Reserved

Register 2

MUT

Left and Right DACs Soft Mute Control

DEM

De-emphasis Control

OPE

Left and Right DACs Operation Control

IW (1:0)

Input Audio Data Bit Select

PL (3:0)

Output Mode Select

A (1:0)

Register Address

res

Reserved

Register 3

Audio Data Format Select

LRP

Polarity of LRCIN (pin 7) Select

ATC

Attenuator Control

SYS

System Clock Select

DSR (1:0)

Double Sampling Rate Select

SF (1:0)

Sampling Rate Select

IZD

Infinite Zero Detection Circuit Control

A (1:0)

Register Address

Res

Reserved

TABLE IV. Internal Register Mapping.

REGISTER 0 (A1 = 0, A0 = 0)

B15 B14 B13 B12 B11 B10 B9

B8

B7 B6

B5 B4 B3

B2 B1

B0

res

res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0

Register 0 is used to control left channel attenuation. Bits

0 - 7 (AL0 - AL7) are used to determine the attenuation

level. The level of attenuation is given by:

ATT = [20 log10 (ATT_DATA/255)] dB