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PCI9060ES 数据表(PDF) 84 Page - List of Unclassifed Manufacturers

部件名 PCI9060ES
功能描述  12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS
PDF  192 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
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标志 ETC - List of Unclassifed Manufacturers

PCI9060ES 数据表(HTML) 84 Page - List of Unclassifed Manufacturers

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SECTION 4
PCI 9080
REGISTERS
©PLX Technology, Inc., 1997
Page 75
Version 1.02
Table 4-58. (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status Register (continued)
Field
Description
Read
Write
Value after Reset
24
Value of 0 indicates a Direct Master was the bus master during a Master or Target
abort. (Not valid until abort occurs.)
Yes
No
1
25
Value of 0 indicates DMA CH 0 was the bus master during a Master or Target
abort. (Not valid until abort occurs.)
Yes
No
1
26
Value of 0 indicates DMA CH 1 was the bus master during a Master or Target
abort. (Not valid until abort occurs.)
Yes
No
1
27
Value of 0 indicates a Target Abort was generated by the PCI 9080 after 256
consecutive Master retries to a Target. (Not valid until abort occurs.)
Yes
No
1
28
Value of 1 indicates PCI wrote data to the MailBox #0. Enabled only if
MBOXINTENB is enabled (bit 3 high).
Yes
No
0
29
Value of 1 indicates PCI wrote data to the MailBox #1. Enabled only if
MBOXINTENB is enabled (bit 3 high).
Yes
No
0
30
Value of 1 indicates PCI wrote data to the MailBox #2. Enabled only if
MBOXINTENB is enabled (bit 3 high).
Yes
No
0
31
Value of 1 indicates PCI wrote data to the MailBox #3. Enabled only if
MBOXINTENB is enabled (bit 3 high).
Yes
No
0



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