Philips Semiconductors

Product data

PCA9535

2003 Jun 27

5

SIMPLIFIED SCHEMATIC OF I/Os

WRITE PULSE

DATA FROM

SHIFT REGISTER

I/O PIN

WRITE CONFIGURATION

PULSE

D

FF

Q

D

Q

FF

D

Q

FF

D

Q

FF

INPUT PORT

REGISTER

POLARITY

INVERSION

REGISTER

OUTPUT

PORT

REGISTER

DATA FROM

SHIFT REGISTER

DATA FROM

SHIFT REGISTER

WRITE

POLARITY

PULSE

CONFIGURATION

REGISTER

OUTPUT PORT

REGISTER DATA

INPUT PORT

REGISTER DATA

POLARITY

REGISTER DATA

READ PULSE

SU01682

Q

Q

Q

Q

TO INT

Q1

Q2

NOTE:

At Power-on Reset, all registers return to default values.

Figure 4. Simplified schematic of I/Os

I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off,

creating a high impedance input. The input voltage may be raised

If the I/O is configured as an output, then either Q1 or Q2 is on,

depending on the state of the Output Port register. Care should be

exercised if an external voltage is applied to an I/O configured as an

output because of the low impedance path that exists between the