TLF5074

January 1988

MM54HC76MM74HC76 Dual J-K Flip-Flops

with Preset and Clear

General Description

These high speed (30 MHz minimum) J-K Flip-Flops utilize

advanced silicon-gate CMOS technology to achieve the low

power consumption and high noise immunity of standard

CMOS integrated circuits along with the ability to drive 10

LS-TTL loads

Each flip-flop has independent J K PRESET CLEAR and

CLOCK inputs and Q and Q outputs These devices are

edge sensitive to the clock input and change state on the

negative going transition of the clock pulse Clear and pre-

set are independent of the clock and accomplished by a low

logic level on the corresponding input

The 54HC74HC logic family is functionally as well as pin-

out compatible with the standard 54LS74LS logic family

All inputs are protected from damage due to static dis-

Features

Y

Typical propagation delay 16 ns

Y

Wide operating voltage range

Y

Low input current 1 mA maximum

Y

Low quiescent current 40 mA maximum (74HC Series)

Y

High output drive 10 LS-TTL loads

Connection and Logic Diagrams

Dual-In-Line Package

TLF5074 – 1

Top View

Order Number MM54HC76 or MM74HC76

Truth Table

Inputs

Outputs

PR

CLR

CLK

J

L

Q

Q

LH

X

X

X

H

L

HL

X

X

X

L

H

LL

X

X

X

L

L

HH

v

L

L

Q0

Q0

HH

v

HL

H

L

HH

v

LH

L

H

HH

v

H

H

TOGGLE

HH

H

X

X

Q0

Q0

This is an unstable condition and is not guaranteed

TLF5074 – 2

(1 of 2)

TLF5074 – 3

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A