SiP823/SiP824/SiP825

Vishay Siliconix

Document Number: 72397

S-41150—Rev. B, 14-Jun-04

www.vishay.com

5

DETAILED DESCRIPTION

An active signal on a microprocessor (mP) RESET input starts

the mP in a know state. The SiP823/SiP824/SiP825 mP

supervisory circuits assert a RESET signal to prevent code

execution errors during power-up, power-down and brown-out

conditions.

The SiP823/SiP824/SiP825 also monitors the mP’s health by

RESET Output

A RESET will be asserted for the specified RESET time-out

2) The MR pin is pulled low

3) The watchdog timer does not detect a transition within the

floating.

The RESET output will remain asserted for the specified

2) MR goes high.

Manual RESET Input

mP based products often require a manual RESET capability,

which can be activated by manual intervention or external logic

circuitry.

A logic low at the MR pin of the SiP823/SiP824/SiP825 asserts

a RESET signal. RESET remains asserted while MR is low

MR has an internal 100-kW pull-up resistor, so it can be left

floating when not activated. This input can be driven with

CMOS logic levels or with open drain devices. The input is

internally de-bounced to reject fast input transients.

Watchdog Input (SiP823/SiP824)

The SiP823/SiP824 have a watchdog input (WDI), that

monitors the mP’s activity. If the mP does not toggle the

RESET is asserted. The internal RESET timer is cleared by

either a RESET pulse or by toggling WDI.

WDI detects pulses as short as 50 nS. While RESET is

asserted, the timer remains cleared. As soon as RESET is

released the timer starts counting (Figure 2).

The watchdog timer can be disabled by leaving WDI open or

by three stating the connected driver. As soon as the WDI input

is driven either high or low, the watchdog function resumes with

the watchdog timer set to zero.

WDI Input Current

The watchdog input pin (WDI) typically sources or sinks 8 mA

when driven high or low.

As a result, the power dissipation at the WDI input is

independent of duty cycle. When the WDI pin is left floating or

tri-stated, the power supply current is less than 3 mA.

Transient Rejection

The SiP823/SiP824/SiP825 family has good immunity for

The smaller the duration of the transient, the larger the

amplitude can be without triggering RESET.

The “Transient Rejection” graph below shows the relation

between transient amplitude and allowable transient duration,

without triggering RESET.

The value on the horizontal scale represents the portion of the

(t1.0 V), the RESET output of the SiP823/SiP824/SiP825

may become undefined. For outputs that are active low

(RESET), a resistor placed between RESET and GND on the

order of 100 kW will ensure that the RESET output stays low

ensure the correct state for active high RESET outputs.