74ALVC541PW datasheet(2/16 Pages) PHILIPS

2 / 16 page

2002 Feb 26

Philips Semiconductors

Product speciﬁcation

Octal buffer/line driver; 3-state

74ALVC541

FEATURES

• Wide supply voltage range from 1.65 to 3.6 V

• Complies with JEDEC standard:

JESD8-7 (1.65 to 1.95 V)

JESD8-5 (2.3 to 2.7 V)

JESD8B/JESD36 (2.7 to 3.6 V).

• 3.6 V tolerant inputs/outputs

• CMOS LOW power consumption

• Direct interface with TTL levels (2.7 to 3.6 V)

• Power-down mode

• Latch-up performance exceeds ≤250 mA

• ESD protection:

2000 V Human Body Model (JESD22-A114-A)

200 V Machine Model (JESD22-A115-A).

DESCRIPTION

The 74ALVC541 is a high-performance, low-power,

low-voltage, Si-gate CMOS device and superior to most

advanced CMOS compatible TTL families.

The 74ALVC541 is an octal non-inverting buffer/line driver

with 3-state bus compatible outputs. The 3-state outputs

are controlled by the output enable inputs OE0 and OE1.

A HIGH on OEn causes the outputs to assume a

high-impedance OFF-state.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C.

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW).

PD =CPD × VCC2 × fi +(CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in Volts.

2. The condition is VI = GND to VCC.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

tPHL/tPLH

propagation delay inputs An to Yn

VCC = 1.8 V; CL = 30 pF; RL =1kΩ

3.0

VCC = 2.5 V; CL = 30 pF; RL = 500 Ω 2.2

VCC = 2.7 V; CL = 50 pF; RL = 500 Ω 2.5

VCC = 3.3 V; CL = 50 pF; RL = 500 Ω 2.3

input capacitance

3.5

CI/O

input/output capacitance

3.5

CPD

power dissipation capacitance per buffer

VCC = 3.3 V; notes 1 and 2

outputs enable

outputs disabled

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