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DS2740U/T 数据表(PDF) 15 Page - Dallas Semiconductor |
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DS2740U/T 数据表(HTML) 15 Page - Dallas Semiconductor |
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15 / 15 page ![]() DS2740 15 of 15 Input Logic Low: DQ, PIO VIL (Note 1) 0.6 V Output Logic Low: DQ, PIO VOL IOL = 4mA (Note 1) 0.4 V DQ, PIO Input Pulldown Current IPD VDD = 4.2V, VDQ = 0.4V 0.5 mA OVD Input Leakage ILOVD PIO bit = 1 -1 1 mA DQ Capacitance CDQ 50 pF DQ Low to Sleep Time tSLEEP (Note 3) 2.0 2.4 s ELECTRICAL CHARACTERISTICS: 1-WIRE INTERFACE—STANDARD SPEED (2.7V £ VDD £ 5.5V; TA = -20°C to +70°C.) PARAMETER SYMBOL MIN TYP MAX UNITS Time Slot tSLOT 60 120 ms Recovery Time tREC 1 ms Write 0 Low Time tLOW0 60 120 ms Write 1 Low Time tLOW1 115 ms Read Data Valid tRDV 15 ms Reset Time High tRSTH 480 ms Reset Time Low tRSTL 480 960 ms Presence Detect High tPDH 15 60 ms Presence Detect Low tPDL 60 240 ms ELECTRICAL CHARACTERISTICS: 1-WIRE INTERFACE—OVERDRIVE SPEED (2.7V £ VDD £ 5.5V; TA = -20°C to +70°C.) PARAMETER SYMBOL MIN TYP MAX UNITS Time Slot tSLOT 616 ms Recovery Time tREC 1 ms Write 0 Low Time tLOW0 616 ms Write 1 Low Time tLOW1 12 ms Read Data Valid tRDV 2 ms Reset Time High tRSTH 48 ms Reset Time Low tRSTL 48 80 ms Presence Detect High tPDH 26 ms Presence Detect Low tPDL 824 ms Note 1: All voltages are referenced to VSS. Note 2: Offset performance requires proper circuit layout design free of surface contaminants. Note 3: The DS2740 enters the sleep mode 2.0s to 2.4s after DQ goes low. |
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