FM3808

Rev 1.1

May 2003

Page 5 of 28

Address

Description

7FF8h

Control-Nonvolatile

D7

D6

D5

D4

D3

D2

D1

D0

OSCEN

Reserved

Reserved

CALS

CAL.3

CAL.2

CAL.1

CAL.0

/OSCEN

/Oscillator Enable. When set to 1, the oscillator is halted. When set to 0, the oscillator runs. Disabling

the oscillator saves battery power during storage. On a no-battery power up, this bit is set to 1. The

RTC will not run until the oscillator is enabled. Set this bit to 0 to activate the RTC.

Reserved

Do not use. Should remain set to 0.

CALS

Calibration sign. Determines if the calibration adjustment is applied as an addition to or as a subtraction

from the time-base. This bit is implemented in FRAM. Calibration is explained below

CAL.3-0

These four bits control the calibration of the clock. These bits are implemented in FRAM.

7FF7h

Watchdog Timer

D7

D6

D5

D4

D3

D2

D1

D0

WDS

WDW

WDT.5

WDT.4

WDT.3

WDT.2

WDT.1

WDT.0

WDS

Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0 has no

affect. The bit is cleared automatically once the watchdog timer is reset. The WDS bit is write only.

Reading it always will return a 0.

/WDW

Watchdog Write Enable. Setting this bit to 1 masks the watchdog timeout value (WDT.5-0) so it cannot

be written. This allows the user to strobe the watchdog without disturbing the timeout value. Setting this

bit to 0 allows bits 5-0 to be written on the next write to the Watchdog register. The new value will be

loaded on the next internal watchdog clock after the write cycle is complete. This function is explained

in more detail in the watchdog Timer section below.

WDT.5-0

Watchdog Timeout selection. The watchdog timer interval is selected by the 6-bit value in this register.

It represents a multiplier of the 32 Hz count (31.25 ms). The minimum range or timeout value is 31.25

ms (a setting of 1) and the maximum timeout is 2 seconds (setting of 3Fh). Setting the watchdog timer

register to 0 disables the timer. These bits can be written only if the /WDW bit was cleared to 0 on a

previous cycle.

7FF6h

Interrupts

D7

D6

D5

D4

D3

D2

D1

D0

WIE

AIE

PFE

ABE

H/L

P/L

Reserved

Reserved

WIE

Watchdog Interrupt Enable. When set to 1 and a watchdog timeout occurs, the watchdog timer drives

the INT pin as well as the WDF flag. When set to 0, the watchdog timeout affects only the WDF flag.

AIE

Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin as well as the AF flag. When

set to 0, the alarm match only affects the AF flag.

PFE

Power-Fail Enable. When set to 1, the power-fail monitor drives the pin as well as the PF flag. When set

to 0, the power-fail monitor affects only the PF flag.

ABE

Alarm Battery-backup Enable. When set to 1, the alarm interrupt (as controlled by AIE) will function

even in battery backup mode. When set to 0, the alarm will occur only when VDD>VLO.

H/L

High/Low. When set to a 1, the INT pin is push/pull active high. When set to a 0, the INT pin is open

drain, active low.

P/L

Pulse/Level. When set to a 1, the INT pin is driven active (determined by H/L) by an interrupt source

for approximately 200 ms. When set to a 0, the INT pin is driven to an active level (as set by H/L) until

the Flags/Control register is read.

7FF5h

Alarm – Date of the month

D7

D6

D5

D4

D3

D2

D1

D0

M

0

10 date.1

10 date.0

Date.3

Date.2

Date.1

Date.0

Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.

/M

Match. Setting this bit to 0 causes the date value to be used in the alarm match. Setting this bit to 1

causes the match circuit to ignore the date value.