Philips Semiconductors

Product data

ADC0803/0804

CMOS 8-bit A/D converters

2002 Oct 17

10

3-STATE TEST CIRCUITS AND WAVEFORMS (ADC0801-1)

90%

50%

10%

10%

GND

GND

RD

DATA

OUTPUT

DATA

OUTPUT

10 k

Ω

CS

RD

90%

50%

10%

90%

GND

GND

RD

DATA

OUTPUT

CS

RD

DATA

OUTPUT

20ns

10 pF

tOH

t1H

10 pF

SL00019

10 k

Ω

Figure 4. 3-State Test Circuits and Waveforms (ADC0801-1)

START

CONVERSION

CS

WR

ACTUAL INTERNAL

STATUS OF THE

CONVERTER

(LAST DATA WAS READ)

(LAST DATA WAS NOT READ)

INTR

INTR

CS

RD

DATA

OUTPUTS

INTR RESET

THREE–STATE

”NOT BUSY”

”BUSY”

DATA IS VALID IN

OUTPUT LATCHES

INT ASSERTED

NOTE

NOTE:

Read strobe must occur 8 clock periods (8/fCLK) after assertion of interrupt to guarantee reset of INTR.

Output Enable and Reset INTR

SL00020

Figure 5. Timing Diagrams