TLF10178

May 1992

54LS192DM74LS192 UpDown Decade Counter

with Separate UpDown Clocks

General Description

The ’LS192 is an updown BCD decade (8421) counter

Separate Count Up and Count Down Clocks are used and in

either counting mode the circuits operate synchronously

The outputs change state synchronous with the LOW-to-

HIGH transitions on the clock inputs

Separate Terminal Count Up and Terminal Count Down out-

puts are provided which are used as the clocks for a subse-

quent stage without extra logic thus simplifying multistage

counter designs Individual preset inputs allow the circuits to

be used as programmable counters Both the Parallel Load

(PL) and the Master Reset (MR) inputs asynchronously

override the clocks

Connection Diagram

Dual-In-Line Package

TLF10178 – 1

Order Number 54LS192DMQB 54LS192FMQB

54LS192LMQB DM74LS192M or DM74LS192N

See NS Package Number E20A J16A

M16A N16E or W16A

Logic Symbol

TLF10178 – 2

Pin Names

Description

Count Up Clock Input

(Active Rising Edge)

Count Down Clock Input

(Active Rising Edge)

MR

Asynchronous Master Reset Input

(Active HIGH)

PL

Asynchronous Parallel Load Input

(Active LOW)

P0 – P3

Parallel Data Inputs

Q0 – Q3

Flip-Flop Outputs

Terminal Count Down (Borrow)

Output (Active LOW)

Terminal Count Up (Carry)

Output (Active LOW)

Mode Select Table

MR

PL

Mode

H

X

X

X

Reset (Asyn)

L

L

X

X

Preset (Asyn)

L

H

H

H

No Change

LH

L

H

Count Up

LH

H

L

Count Down

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A