TLF6638

June 1989

DM54L95 4-Bit Parallel Access Shift Registers

General Description

These 4-bit registers feature parallel and serial inputs paral-

lel output mode control and two clock inputs The registers

have three modes of operation

Parallel (broadside) load

Parallel loading is accomplished by applying the four bits of

data and taking the mode control input high The data is

loaded into the associated flip-flops and appears at the out-

puts after the high-to-low transition of the clock-2 input Dur-

ing loading the entry of serial data is inhibited

Shift right is accomplished on the high-to-low transition of

clock 1 when the mode control is low shift left is accom-

plished on the high-to-low transition of clock 2 when the

mode control is high by connecting the output of each flip-

C etc) and serial data is entered at input D The clock input

may be applied simultaneously to clock 1 and clock 2 if both

modes can be clocked from the same source

Changes at the mode control input should normally be

made while both clock inputs are low however conditions

described in the last three lines of the truth table will also

ensure that register contents are protected

Features

Y

Typical maximum clock frequency 14 MHz

Y

Typical power dissipation mW

Connection Diagram

Dual-In-Line Package

TLF6638 – 1

Order Number DM54L95J

or DM54L95W

See NS Package Number

J14A or W14B

Function Table

Inputs

Outputs

Mode

Clocks

Serial

Parallel

Control

2 (L)

1 (R)

A

B

C

D

HH

X

X

X

X

X

X

H

v

XX

a

b

c

d

a

b

c

d

H

v

XX

d

LL

H

X

X

X

X

X

LX

v

HX

X

X

X

H

LX

v

LX

X

X

X

L

u

LL

X

X

X

X

X

v

LL

X

X

X

X

X

v

LH

X

X

X

X

X

u

HL

X

X

X

X

X

u

HH

X

X

X

X

X

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A