Symbol

Parameter

DM54LS

DM74LS

Units

Min

Max

Min

Max

Maximum Clock Frequency

30

30

MHz

Propagation Delay

24

24

ns

24

24

Propagation Delay

27

27

ns

Functional Description

The ’LS273 is an 8-bit parallel register with a common Clock

and common Master Reset When the MR input is LOW the

Q outputs are LOW independent of the other inputs Infor-

mation meeting the setup and hold time requirements of the

D inputs is transferred to the Q outputs on the LOW-to-

HIGH transition of the clock input

Truth Table

Inputs

Outputs

MR

CP

LX

X

L

H

L

HH

H

L

LL

Logic Symbol

TLF9825 – 2

Logic Diagram

TLF9825 – 3

3