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CY22381SI-RGLT 数据表(PDF) 4 Page - Cypress Semiconductor

部件名 CY22381SI-RGLT
功能描述  Three-PLL General Purpose FLASH Programmable Clock Generator
PDF  8 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

CY22381SI-RGLT 数据表(HTML) 4 Page - Cypress Semiconductor

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CY22381
Document #: 38-07012 Rev. *D
Page 4 of 8
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Supply Voltage ............................................... –0.5V to +7.0V
DC Input Voltage.............................. –0.5V to + (VDD + 0.5V)
Storage Temperature ..................................–65°C to +125°C
Junction Temperature .................................................. 125°C
Data Retention @ Tj = 125°C................................> 10 years
Maximum Programming Cycles........................................100
Package Power Dissipation...................................... 250 mW
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ...........................
≥ 2000V
Latch up (per JEDEC 17) ....................................
±200 mA
Operating Conditions[1]
Parameter
Description
Min.
Typ.
Max.
Unit
VDD
Supply Voltage
3.135
3.3
3.465
V
TA
Commercial Operating Temperature, Ambient
0
+70
°C
Industrial Operating Temperature, Ambient
–40
+85
°C
CLOAD_OUT
Max. Load Capacitance
15
pF
fREF
External Reference Crystal
8
30
MHz
External Reference Clock[2], Commercial
1
166
MHz
External Reference Clock[2], Industrial
1
150
MHz
tPU
Power-up time for all VDD's to reach minimum specified voltage
(power ramps must be monotonic)
0.05
500
ms
Electrical Characteristics
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
IOH
Output High Current[3]
VOH = VDD –0.5, VDD =3.3 V
12
24
mA
IOL
Output Low Current[3]
VOL = 0.5V, VDD =3.3 V
12
24
mA
CXTAL_MIN
Crystal Load Capacitance[3]
Capload at minimum setting
6
pF
CXTAL_MAX
Crystal Load Capacitance[3]
Capload at maximum setting
30
pF
CIN
Input Pin Capacitance[3]
Except crystal pins
7
pF
VIH
HIGH-level Input Voltage
CMOS levels,% of VDD
70%
VDD
VIL
LOW-level Input Voltage
CMOS levels,% of VDD
30%
VDD
IIH
Input HIGH Current
VIN =VDD –0.3 V
<1
10
µA
IIL
Input LOW Current
VIN =+0.3V
<1
10
µA
IOZ
Output Leakage Current
Three-state outputs
10
µA
IDD
Total Power Supply Current
3.3 V Power Supply; 3 outputs @ 50 MHz
35
mA
3.3 V Power Supply; 3 outputs @ 166 MHz
70
mA
IDDS
Total Power Supply Current in
Shutdown Mode
Shut-down active
5
20
µA
Notes:
1. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.
2. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2.
3. Guaranteed by design, not 100% tested.



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