Functional Description

The ’LS299 contains eight edge-triggered D-type flip-flops

and the interstage logic necessary to perform synchronous

shift left shift right parallel load and hold operations The

type of operation is determined by the S0 and S1 as shown

in the Mode Select Table All flip-flop outputs are brought

out through TRI-STATE buffers to separate IO pins that

also serve as data inputs in the parallel load mode Q0 and

Q7 are also brought out on other pins for expansion in serial

shifting of longer words

A LOW signal on MR overrides the Select and CP inputs

and resets the flip-flops All other state changes are initiated

by the rising edge of the clock Inputs can change when the

clock is in either state provided only that the recommended

setup and hold times relative to the rising edge of CP are

observed

A HIGH signal on either OE1orOE2 disables the TRI-

STATE buffers and puts the IO pins in the high impedance

state In this condition the shift hold load and reset opera-

tions can still occur The TRI-STATE buffers are also dis-

abled by HIGH signals on both S0 and S1 in preparation for

a parallel load operation

Mode Select Table

Inputs

Response

MR S1 S0 CP

L

X

X

X

HH

H

HL

H

HH

L

H

L

L

X

Hold

4