TLF10189

April 1992

DM54LS502DM74LS502

8-Bit Successive Approximation Register

General Description

The LS502 is an 8-bit register with the interstage logic nec-

essary to perform serial-to-parallel conversion and provide

an active LOW Conversion Complete (CC) signal coincident

with storage of the eighth bit An active LOW Start (S) input

performs synchronous initialization which forces Q7 LOW

and all other outputs HIGH Subsequent clocks shift this Q7

LOW signal downstream which simultaneously backfills the

register such that the first serial data (D input) bit is stored in

Q7 the second bit in Q6 the third in Q5 etc The serial

input data is also synchronized by an auxiliary flip-flop and

Designed primarily for use in the successive approximation

technique for analog-to-digital conversion the LS502 can

also be used as a serial-to-parallel converter ring counter

and as the storage and control element in recursive digital

routines

Features

Y

Low power Schottky version of 2502

Y

Storage and control for successive approximation A to

D conversion

Y

Performs serial-to-parallel conversion

Connection Diagram

Dual-In-Line Package

TLF10189 – 1

Order Number DM54LS502J DM54LS502W

DM74LS502WM or DM74LS502N

See NS Package Number J16A M16B N16E or W16A

Logic Symbol

TLF10189 – 2

Pin

Description

Names

D

Serial Data Input

S

Start Input (Active LOW)

CP

Clock Pulse Input (Active Rising Edge)

Synchronized Serial Data Output

CC

Conversion Complete Output (Active LOW)

Q0 – Q7

Parallel Register Outputs

Q7

Complement of Q7 Output

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A