TLF9827

June 1992

DM54LS299DM74LS299

8-Input Universal ShiftStorage Register

with Common Parallel IO Pins

General Description

The ’LS299 is an 8-bit universal shiftstorage register with

TRI-STATE

outputs Four modes of operation are possi-

ble hold (store) shift left shift right and load data The par-

allel load inputs and flip-flop outputs are multiplexed to re-

duce the total number of package pins Separate outputs

are provided for flip-flops Q0 and Q7 to allow easy cascad-

ing A separate active LOW Master Reset is used to reset

the register

Features

Y

Common IO for reduced pin count

Y

Four operation modes shift left shift right load and

store

Y

Separate shift right serial input and shift left serial input

for easy cascading

Y

TRI-STATE outputs for bus oriented applications

Connection Diagram

Dual-In-Line Package

TLF9827 – 1

Order Number DM54LS299E DM54LS299J DM54LS299W

DM74LS299WM or DM74LS299N

See NS Package Number E20A J20A M20B N20A or W20A

Pin Names

Description

CP

Clock Pulse Input (Active Rising Edge)

Serial Data Input for Right Shift

Serial Data Input for Left Shift

S0 S1

Mode Select Inputs

MR

Asynchronous Master Reset Input

(Active LOW)

OE1 OE2

TRI-STATE Output Enable Inputs

(Active LOW)

IO0 – IO7

Parallel Data Inputs or TRI-STATE

Parallel Outputs

Q0 – Q7

Serial Outputs

TRI-STATE

is a registered trademark of National Semiconductor Corporation

C1995 National Semiconductor Corporation

RRD-B30M115Printed in U S A