ADS7253IPWR datasheet(39/71 Pages) TI1

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SCLK

ADS8353, ADS8354

SDO_A and SDO_B

Sample

N + 1

tACQ

tCONV

tTHROUGHPUT

Data From Sample N

D15

D14

Data From Sample N

B15

B14

SDI

tSCLK

ADS7853, ADS7854

SDO_A and SDO_B

ADS7253, ADS7254

SDO_A and SDO_B

D13

D12

D11

D10

ADS8353, ADS7853, ADS7253

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SBAS584B – OCTOBER 2013 – REVISED AUGUST 2014

8.5.3.2 Conversion Data Read

The device provides four different interface modes to the user for reading the conversion result. These modes

offer flexible hardware connections and firmware programming. Table 11 shows how to select one of the four

interface modes.

Table 11. Interface Mode Selection

MINIMUM SCLK FALLING EDGES

CFR.B11

CFR.B10

INTERFACE MODE

REQUIRED TO VALIDATE WRITE

OPERATION N

32-CLK, dual-SDO mode (default)

32-CLK, single-SDO mode

16-CLK, dual-SDO mode

16-CLK, single SDO mode

In the 32-CLK interface modes, the device uses an internal clock to convert the sampled analog signal. The

conversion is completed during the first 16 periods of SCLK and the conversion result can be read on the

subsequent SCLK falling edges. All devices in the family (that is, ADS8353, ADS7853, and ADS7253) support

the 32-CLK interface modes.

In addition to the 32-CLK interface modes, the ADS7853 and ADS7253 also support the 16-CLK interface

modes. By using the 16-CLK interface modes, the same throughput can be achieved at much lower SCLK

speeds.

The following sections detail the various interface modes supported by the device.

8.5.3.2.1

32-CLK, Dual-SDO Mode (CFR.B11 = 0, CFR.B10 = 0, Default)

The 32-CLK, dual-SDO mode is the default mode supported by all devices. This mode can also be selected by

writing CFR.B11 = 0 and CFR.B10 = 0.

In this mode, the SDO_A pin outputs the ADC_A conversion result and the SDO_B pin outputs the ADC_B

conversion result. Figure 91 shows a detailed timing diagram for this mode.

Figure 91. 32-CLK, Dual-SDO Mode Timing Diagram

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Product Folder Links: ADS8353 ADS7853 ADS7253

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