BQ20Z95DBT datasheet(7/21 Pages) TI1

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bq20z95

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SLUS757C – JULY 2007 – REVISED OCTOBER 2013

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V, V(BAT) =

14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

HARDWARE SHORT CIRCUIT AND OVERLOAD PROTECTION; TA = 25°C (unless otherwise noted)

VOL = 25 mV (min)

OL detection threshold voltage

V(OL)

VOL = 100 mV; RSNS = 0, 1

100

110

accuracy

VOL = 205 mV (max)

185

205

225

V(SCC) = 50 mV (min)

SCC detection threshold voltage

V(SCC)

V(SCC) = 200 mV; RSNS = 0, 1

180

200

220

accuracy

V(SCC) = 475 mV (max)

428

475

523

V(SCD) = –50 mV (min)

–30

–50

–70

SCD detection threshold voltage

V(SCD)

V(SCD) = –200 mV; RSNS = 0, 1

–180

–200

–220

accuracy

V(SCD) = –475 mV (max)

–428

–475

–523

tda

Delay time accuracy

±15.25

μs

tpd

Protection circuit propagation delay

μs

FET DRIVE CIRCUIT; TA = 25°C (unless otherwise noted)

V(DSGON) = V(DSG) – V(PACK); V(GS) = 10 MΩ; DSG and

V(DSGON)

DSG pin output on voltage

CHG on;

TA = –40°C to 100°C

V(CHGON) = V(CHG) – V(BAT); V(GS) = 10 MΩ; DSG and

V(CHGON)

CHG pin output on voltage

CHG on;

TA = –40°C to 100°C

V(DSGOFF)

DSG pin output off voltage

V(DSGOFF) = V(DSG) – V(PACK)

0.2

V(CHGOFF)

CHG pin output off voltage

V(CHGOFF) = V(CHG) – V(BAT)

0.2

CL= 4700 pF; V(PACK) ≤ DSG ≤ V(PACK) + 4V

400

1000

Rise time

μs

CL= 4700 pF; V(BAT) ≤ CHG ≤ V(BAT) + 4V

400

1000

CL= 4700pF; V(PACK) + V(DSGON) ≤ DSG ≤ V(PACK) + 1V

200

Fall time

μs

CL= 4700 pF; V(BAT) + V(CHGON) ≤ CHG ≤ V(BAT) + 1 V

200

V(ZVCHG)

ZVCHG clamp voltage

BAT = 4.5 V

3.3

3.5

3.7

LOGIC; TA = –40°C to 100°C (unless otherwise noted)

ALERT

100

200

R(PULLUP)

Internal pullup resistance

Ω

RESET

ALERT

0.2

VOL

Logic low output voltage level

RESET; V(BAT) = 7V; V(REG25) = 1.5 V; I (RESET) = 200 μA

0.4

GPOD; I(GPOD) = 50 μA

0.6

LOGIC SMBC, SMBD, PFIN, PRES, SAFE, ALERT

VIH

High-level input voltage

2.0

VIL

Low-level input voltage

0.8

VREG25–0

VOH

Output voltage high(1)

IL = –0.5 mA

VOL

Low-level output voltage

PRES, PFIN, ALERT, IL = 7 mA;

0.4

Input capacitance

I(SAFE)

SAFE source currents

SAFE active, SAFE = V(REG25) –0.6 V

–3

Ilkg(SAFE)

SAFE leakage current

SAFE inactive

–0.2

0.2

µA

Ilkg

Input leakage current

µA

ADC(2)

Input voltage range

TS1, TS2, using Internal Vref

–0.2

Conversion time

31.5

Resolution (no missing codes)

bits

Effective resolution

bits

Integral nonlinearity

±0.03

%FSR(3)

(1)

RC[0:7] bus

(2)

Unless otherwise specified, the specification limits are valid at all measurement speed modes.

(3)

Full-scale reference

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