CC1100-RTY1 datasheet(25/100 Pages) TI1

25 / 100 page

CC1100

SWRS038D

Page 25 of 92

the SLEEP or XOFF states, the SO pin will

always go low immediately after taking CSn

low.

Figure 7: Configuration Registers Write and Read Operations

Parameter

Description

Min

Max

Units

SCLK frequency

100 ns delay inserted between address byte and data byte (single access), or

between address and data, and between each data byte (burst access).

SCLK frequency, single access

No delay between address and data byte

fSCLK

SCLK frequency, burst access

No delay between address and data byte, or between data bytes

6.5

MHz

tsp,pd

CSn low to positive edge on SCLK, in power-down mode

150

µs

tsp

CSn low to positive edge on SCLK, in active mode

tch

Clock high

tcl

Clock low

trise

Clock rise time

tfall

Clock fall time

tsd

Setup data (negative SCLK edge) to

positive edge on SCLK

(tsd applies between address and data bytes, and between

data bytes)

Single access

Burst access

thd

Hold data after positive edge on SCLK

tns

Negative edge on SCLK to CSn high.

Table 16: SPI Interface Timing Requirements

Note:

The minimum tsp,pd figure in Table 16 can be used in cases where the user does not read the

CHIP_RDYn

signal. CSn low to positive edge on SCLK when the chip is woken from power-down

depends on the start-up time of the crystal being used. The 150 us in Table 16 is the crystal oscillator

start-up time measured on CC1100EM reference designs ([5] and [6]) using crystal AT-41CD2 from

NDK.

CC1100-RTY1 数据表(PDF) 25 Page - Texas Instruments

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