CC1150-RTY1 datasheet(25/67 Pages) TI1

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Packet

Engine

FEC

Encoder

Modulator

Interleaver

Write buffer

Interleaver

Read buffer

Demodulator

FEC

Decoder

Packet

Engine

Interleaver

Write buffer

Interleaver

Read buffer

CC1150

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SWRS037B – JANUARY 2006 – REVISED MARCH 2015

5.10.2 Interleaving

Data received through real radio channels will often experience burst errors due to interference and time-

varying signal strengths. In order to increase the robustness to errors spanning multiple bits, interleaving

is used when FEC is enabled. After de-interleaving, a continuous span of errors in the received stream will

become single errors spread apart.

CC1150 employs matrix interleaving, which is illustrated in Figure 5-10. The on-chip interleaving buffer is

a 4 × 4 matrix. In the transmitter, the data bits are written into the rows of the matrix, whereas the bit

sequence to be transmitted is read from the columns of the matrix and fed to the rate ½ convolutional

coder. Conversely, in a CC1101 receiver, the received symbols are written into the rows of the matrix,

whereas the data passed onto the convolutional decoder is read from the columns of the matrix.

When FEC and interleaving is used, at least one extra byte is required for trellis termination. In addition,

the amount of data transmitted over the air must be a multiple of the size of the interleaver buffer (two

bytes). The packet control hardware therefore automatically inserts one or two extra bytes at the end of

the packet, so that the total length of the data to be interleaved is an even number. Note that these extra

bytes are invisible to the user, as they are removed before the received packet enters the RX FIFO in a

CC1101.

When FEC and interleaving is used, the minimum data payload is 2 bytes in fixed and variable packet

length mode.

Figure 5-10. : General Principle of Matrix Interleaving

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