AMC7836IPAPR datasheet(33/88 Pages) TI1

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ALARM STATUS 0

0x70

RESERVED

LV_ADC20 Alarm

LV_ADC19 Alarm

LV_ADC18 Alarm

LV_ADC17 Alarm

LV_ADC16 Alarm

ALARM STATUS 1

0x71

RESERVED

ALARMIN Alarm

Die Temperature Alarm

Temperature Sensor High Alarm

Temperature Sensor Low Alarm

GALR

AMC7836

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SLAS986C – NOVEMBER 2014 – REVISED APRIL 2016

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7.3.2.4 Programmable Out-of-Range Alarms

The AMC7836 device is capable of continuously analyzing the five external unipolar inputs and internal

temperature sensor conversion results for normal operation.

Normal operation is established through the lower and upper threshold registers (address 0x80 through 0x97).

When any of the monitored inputs is out of the specified range, an alarm event is issued and the global alarm bit,

GALR in the general status register (0x72), is set (see Figure 54). Use the alarm status registers (0x70 through

0x71) to determine the source of the alarm event.

Figure 54. Alarm Status Register

The ALARM-LATCH-DIS bit in the ALARMOUT source 1 register (address 0x1D) sets the latching behavior for

all alarms (except for the ALARMIN alarm which is always unlatched). When the ALARM-LATCH-DIS bit is

cleared to 0 the alarm bits in the alarm status registers are latched. The alarm bits are referred to as being

latched because they remain set until read by software. This design ensures that out-of-limit events cannot be

missed if the software is polling the device periodically. All bits are cleared when reading the alarm status

registers, and all bits are reasserted if the out-of limit condition still exists on the next monitoring cycle, unless

otherwise noted. When the ALARM-LATCH-DIS bit is set to 1, the alarm bits are not latched. The alarm bits in

the alarm status registers are set to 0 when the error condition subsides, regardless of whether the bit is read or

not.

All of the alarms can be set to activate the ALARMOUT pin. To enable this functionality, the GPIO1/ALARMOUT

pin must be configured accordingly in the GPIO configuration register (address 0x12). The ALARMOUT pin

works as an interrupt to the host so that it can query the alarm status registers to determine the alarm source.

Any alarm event can activate the pin as long as the alarm is not masked in the ALARMOUT source registers

(address 0x1C through 0x1D). When an alarm event is masked, the occurrence of the event sets the

corresponding status bit in the alarm status registers, but does not activate the ALARMOUT pin.

AMC7836IPAPR 数据表(PDF) 33 Page - Texas Instruments

AMC7836IPAPR 数据表(HTML) 33 Page - Texas Instruments

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