DP83256VF datasheet(49/144 Pages) NSC

49 / 144 page

50 Registers (Continued)

Bit

Symbol

Description

D3 D4

IC0 IC1

Injection Control k0 1l

These bits select one of the 4 injection modes The injection modes have priority

over data from the Smoother Repeat Filter Encoder and Transmit Modes

IC0 is the only bit of the register that is automatically cleared by the PLAYERa device after the One Shot

Injection is executed The automatic clear of IC0 during the One Shot mode can be interpreted as a

acknowledgment that the One Shot has been completed

IC1

IC0

No Injection

The normal transmission of incoming PHY Request data (ie symbols are not

injected)

One Shot

In one shot mode the contents of Injection Symbol Register A (ISRA) and Injection

Symbol Register B (ISRB) are injected n symbol pairs after a JK where n is the programmed

value of the Injection Count Register (IJCR) If IJCR is set to 0 the JK symbol pair is replaced by

ISRA and ISRB Once the One Shot is executed the PLAYERa device automatically sets IC0 to

0 thereby returning to normal transmission of data

Periodic

In Periodic mode the contents of Injection Symbol Register A (ISRA) and Injection

Symbol Register B (ISRB) are injected every n-th symbol pair where n is the programmed value

of the Injection Count Register (IJCR) If IJCR is set to 0 all data symbols are replaced with ISRA

and ISRB

Note

The inserted symbol is not automatically aligned to a JK boundary

Continuous

In Continuous mode all data symbols are replaced with the contents of Injection

Symbol Register A (ISRA) and Injection Symbol Register B (ISRB)

SMOOTHER ENABLE

Disables the Smoother

Enables the Smoother

When enabled the Smoother can redistribute Idle symbol pairs which were added or deleted by the

local or upstream receivers

Note

Once the counter has started it will continue to count irrespective of the incoming symbols with the exception of a JK symbol pair

PRDPE

PHY

REQUEST DATA PARITY ENABLE

Disables PHY

Request Data parity

Enables PHY

Request Data parity

RES

RESERVED

Reserved for future use

Note

Users are discouraged from using this bit The reserved bit is set to 1 during the reset process It may be set or cleared without any

effects to the functionality of the PLAYERa device

DP83256VF 数据表(PDF) 49 Page - National Semiconductor (TI)

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DP83256VF 数据表(PDF) 49 Page - National Semiconductor (TI)

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