2003 May 26

10

Philips Semiconductors

Product specification

Dual D-type flip-flop with set and reset;

positive-edge trigger

74ALVC74

handbook, full pagewidth

MNA423

trem

tPHL

tPHL

tW

tPLH

tPLH

VM

VM

VM

tW

VM

VM

VI

GND

VI

GND

nSD input

VI

GND

nRD input

nCP input

VOH

VOL

nQ output

VOH

VOL

nQ output

Fig.7

The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths

and the nRD to nCP removal time.

INPUT

1.65 to 1.95 V

0.5

≤ 2.0 ns

2.3 to 2.7 V

0.5

× V

CC

≤ 2.0 ns

2.7 V

1.5 V

2.7 V

≤ 2.5 ns

3.0 to 3.6 V

1.5 V

2.7 V

≤ 2.5 ns