DAC8564D datasheet(39/51 Pages) TI1

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SYNC

DAC8564(1)

SCLK

NOTE:(1)Additionalpinsomittedforclarity.

Microwire

(1)

PC7

SCK

MOSI

SYNC

DAC8564(1)

SCLK

NOTE:(1)Additionalpinsomittedforclarity.

68HC11

(1)

P3.3

TXD

RXD

SYNC

DAC8564(1)

SCLK

NOTE:(1)Additionalpinsomittedforclarity.

80C51/80L51

(1)

DAC8564

www.ti.com

SBAS403D

– JUNE 2007 – REVISED MAY 2011

DAC8564 to Microwire Interface

MICROPROCESSOR INTERFACING

Figure 102 shows an interface between the DAC8564

DAC SPI Interfacing

and any Microwire-compatible device. Serial data are

shifted out on the falling edge of the serial clock and

Care must be taken with the digital control signals

are clocked into the DAC8564 on the rising edge of

that are applied directly to the DAC, especially with

the SK signal.

the SYNC pin. The SYNC pin must not be toggled

without having a full SCLK pulse in between. If this

condition is violated, the SPI interface locks up in an

erroneous

state,

causing

the

DAC

behave

incorrectly and have errors. The DAC can be

recovered from this faulty state by writing a valid SPI

command

using

the

SYNC

correctly;

communication will then be restored. Avoid glitches

and transients on the SYNC line to ensure proper

operation.

Figure 102. DAC8564 to Microwire Interface

DAC8564 to an 8051 Interface

Figure 101 shows a serial interface between the

DAC8564 to 68HC11 Interface

DAC8564 and a typical 8051-type microcontroller.

The setup for the interface is as follows: TXD of the

Figure 103 shows a serial interface between the

8051 drives SCLK of the DAC8564, while RXD drives

DAC8564 and the 68HC11 microcontroller. SCK of

the serial data line of the device. The SYNC signal is

the 68HC11 drives the SCLK of the DAC8564, while

derived from a bit-programmable pin on the port of

the MOSI output drives the serial data line of the

the 8051; in this case, port line P3.3 is used. When

DAC. The SYNC signal derives from a port line

data are to be transmitted to the DAC8564, P3.3 is

(PC7), similar to the 8051 diagram.

taken low. The 8051 transmits data in 8-bit bytes;

thus, only eight falling clock edges occur in the

transmit cycle. To load data to the DAC, P3.3 is left

low after the first eight bits are transmitted; then, a

second write cycle is initiated to transmit the second

byte of data. P3.3 is taken high following the

completion of the third write cycle. The 8051 outputs

the serial data in a format that has the LSB first. The

DAC8564 requires its data with the MSB as the first

bit received. The 8051 transmit routine must therefore

Figure 103. DAC8564 to 68HC11 Interface

take this requirement into account, and mirror the

data as needed.

The 68HC11 should be configured so that its CPOL

bit is '0' and its CPHA bit is '1'. This configuration

causes data appearing on the MOSI output to be

valid on the falling edge of SCK. When data are

being transmitted to the DAC, the SYNC line is held

low

(PC7).

Serial

data

from

the

68HC11

are

transmitted in 8-bit bytes with only eight falling clock

edges occurring in the transmit cycle. (Data are

transmitted MSB first.) In order to load data to the

DAC8564, PC7 is left low after the first eight bits are

Figure 101. DAC8564 to 80C51/80L51 Interface

transferred; then, a second and third serial write

operation are performed to the DAC. PC7 is taken

high at the end of this procedure.

DAC8564D 数据表(PDF) 39 Page - Texas Instruments

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