DAC8564 datasheet(27/47 Pages) TI1

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DAC8165

www.ti.com

SBAS409B

– FEBRUARY 2008 – REVISED MARCH 2011

SERIAL INTERFACE

be kept LOW or brought HIGH. In either case, the

minimum delay time from the 24th falling SCLK edge

The DAC8165 has a 3-wire serial interface (SYNC,

to the next falling SYNC edge must be met in order to

SCLK, and DIN) compatible with SPI, QSPI, and

properly begin the next cycle. To assure the lowest

Microwire interface standards, as well as most DSPs.

power consumption of the device, care should be

See the Serial Write Operation timing diagram for an

taken that the levels are as close to each rail as

example of a typical write sequence.

possible. Refer to the Typical Characteristics section

for Figure 36, Figure 57, and Figure 79 (Supply

The DAC8165 input shift register is 24 bits wide,

Current vs Logic Input Voltage).

consisting of eight control bits (DB23 to DB16) and 14

data bits (DB15 to DB2). Bits DB0 and DB1 are

ignored by the DAC and should be treated as don't

IOVDD AND VOLTAGE TRANSLATORS

care bits. All 24 bits of data are loaded into the DAC

The IOVDD pin powers the the digital input structures

under the control of the serial clock input, SCLK.

of the DAC8165. For single-supply operation, it can

DB23 (MSB) is the first bit that is loaded into the DAC

be tied to AVDD. For dual-supply operation, the IOVDD

shift register, and is followed by the rest of the 24-bit

pin provides interface flexibility with various CMOS

word pattern, left-aligned. This configuration means

logic families and should be connected to the logic

that the first 24 bits of data are latched into the shift

supply of the system. Analog circuits and internal

logic of the DAC8165 use AVDD as the supply

The DAC8165 receives all 24 bits of data and

voltage. The external logic high inputs translate to

decodes the first eight bits to determine the DAC

AVDD by level shifters. These level shifters use the

operating/control mode. The 14 bits of data that

IOVDD voltage as a reference to shift the incoming

follow are decoded by the DAC to determine the

logic HIGH levels to AVDD. IOVDD is ensured to

equivalent analog output, while the last two bits (DB1

operate from 2.7V to 5.5V regardless of the AVDD

and DB0) are ignored. The data format is straight

voltage, assuring compatibility with various logic

binary with all '0's corresponding to 0V output and all

families. Although specified down to 2.7V, IOVDD

'1's corresponding to full-scale output (that is, VREF –

operates at as low as 1.8V with degraded timing and

1 LSB); see the Data Format section for more details.

temperature

performance.

For

lowest

power

For all documentation purposes, the data format and

consumption, logic VIH levels should be as close as

representation here is a true 14-bit pattern (that is,

possible to IOVDD, and logic VIL levels should be as

3FFFh for full-scale), even if the usable 14 bits of

close as possible to GND voltages.

data are extracted from a left-justified 16-bit data

format that the DAC8165 requires.

ASYNCHRONOUS RESET

The write sequence begins by bringing the SYNC line

The DAC8165 output is asynchronously set to

low. Data from the DIN line are clocked into the 24-bit

zero-scale voltage or mid-scale voltage (depending

shift register on each falling edge of SCLK. The serial

on RSTSEL) immediately after the RST pin is brought

clock frequency can be as high as 50MHz, making

low. The RST signal resets all internal registers, and

the DAC8165 compatible with high-speed DSPs. On

therefore, behaves like the Power-On Reset. The

the 24th falling edge of the serial clock, the last data

RST pin must be brought back to high before a write

bit is clocked into the shift register and the shift

sequence starts. If the RSTSEL pin is high, the RST

signal going low resets all outputs to mid-scale. If the

shift register data. After 24 bits are locked into the

RSTSEL pin is low, the RST signal going low resets

shift register, the eight MSBs are used as control bits

all outputs to zero-scale. RSTSEL should be set at

and the following 14 LSBs are used as data. After

power-up.

receiving the 24th falling clock edge, the DAC8165

decodes the eight control bits and 14 data bits to

INPUT SHIFT REGISTER

perform the required function, without waiting for a

SYNC rising edge. A new write sequence starts at the

The input shift register (SR) of the DAC8165 is 24

next falling edge of SYNC. A rising edge of SYNC

bits wide, as shown in Table 5, and consists of eight

before the 24-bit sequence is complete resets the SPI

control bits (DB23 to DB16), 12 data bits (DB15 to

interface; no data transfer occurs. After the 24th

DB4), and four don't care bits. DB23 and DB22

falling edge of SCLK is received, the SYNC line may

should always be '0'.

Table 5. Data Input Register Format

DB23

DB12

LD1

LD0

DAC Select 1

DAC Select 0

PD0

D13

D12

D11

D10

DB11

DB0

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