CDC2509

3.3V PHASELOCK LOOP CLOCK DRIVER

SCAS580C − OCTOBER 1996 − REVISED DECEMBER 2004

7

POST OFFICE BOX 655303

TYPICAL CHARACTERISTICS

Figure 3

PHASE ERROR

vs

CLOCK FREQUENCY

35

−0.3

−0.5

−0.7

−0.9

45

55

65

95

105

fclk − Clock Frequency − MHz

85

−0.2

−0.4

−0.6

−0.8

75

115 125

VDD = 3.3 V

TA = 25°C

−0.1

0

25

Figure 4

VDD = 3.3 V

CL = 30 pF

OUTPUT DUTY CYCLE

vs

CLOCK FREQUENCY

57%

53%

51%

47%

43%

55%

49%

45%

40

50

60

70

100 110

fclk − Clock Frequency − MHz

90

80

120 130

30

ANALOG SUPPLY CURRENT

vs

CLOCK FREQUENCY

35

6

4

2

0

45

55

65

95

105

fclk − Clock Frequency − MHz

85

7

5

3

1

75

115 125

VDD = 3.3 V

TA = 25°C

8

9

25

Figure 5

0

50

100

150

200

250

20

40

60

80

100

120

140

SUPPLY CURRENT

vs

CLOCK FREQUENCY

fclk − Clock Frequency − MHz

VCC = 3.6 V

TA = 25°C

CLY = CLF = 30 pF

Figure 6