1

2

C

B

A

A1

A2

B2

C2

D2

B1

C1

D1

D

CDC3RL02

www.ti.com

SCHS371C – NOVEMBER 2009 – REVISED JANUARY 2016

5 Device Comparison Table

BACKSIDE

ORDERABLE PART NUMBER

-40 C to 85 C

YFP

CDC3RL02BYFPR

Yes

-40 C to 85 C

YFP

CDC3RL02YFPR

No

(1)

Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(2)

CSP (DSBGA) devices manufactured with backside coating have an increased resistance to cracking due to the increased physical

strength of the package. Devices with backside coating are highly encouraged for new designs.

6 Pin Configuration and Functions

YFP Package

8-Pin DSBGA

Top View

Pin Functions

PIN

I/O

DESCRIPTION

NAME

NO.

A1

I

Input to internal LDO

CLK_OUT1

A2

O

Clock output 1

B1

O

1.8 V I/O supply for CDC3RL02 and external TCXO

CLK_REQ1

B2

I

Clock request from peripheral 2

MCLK_IN

C1

I

Master clock input

CLK_REQ2

C2

I

Clock request from peripheral 1

GND

D1

–

Ground

CLK_OUT2

D2

O

Clock output 2

YFP Package Pin Assignments

1

2

A

CLK_OUT1

B

CLK_REQ1

C

MCLK_LIN

CLK_REQ2

D

GND

CLK_OUT2

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