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AD1985 数据表(PDF) 32 Page - Analog Devices |
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AD1985 数据表(HTML) 32 Page - Analog Devices |
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32 / 48 page ![]() AD1985 Rev. A | Page 32 of 48 SPDIF Control Register (Index 0x3A) Reg.Num. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x3A SPDIF Control V X SPSR1 SPSR0 L CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY AUD PRO 0x2000 Register 0x3A is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe in the V case). With the exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF bit in Register 0x2A is 0). This ensures that control and status information initialize correctly at the beginning of SPDIF transmission. PRO Professional. 1 indicates professional use of channel status, 0 indicates consumer. AUD Nonaudio. 1 indicates data is nonPCM format, 0 indicates data is PCM. COPY Copyright. 1 indicates copyright is asserted, 0 indicates copyright is not asserted. PRE Pre-emphasis. 1 indicates filter pre-emphasis is 50/15 µs, 0 indicates no pre-emphasis. CC[6:0] Category Code. Programmed according to IEC standards, or as appropriate. L Generation Level. Programmed according to IEC standards, or as appropriate. SPSR[1:0] SPDIF Transmit Sample Rate. SPSR[1:0] = 00: Transmit Sample Rate = 44.1 kHz. SPSR[1:0] = 01: Reserved. SPSR[1:0] = 10: Transmit Sample Rate = 48 kHz (default). SPSR[1:0] = 11: Not supported. V Validity. This bit affects the Validity flag (Bit <28> transmitted in each SPDIF L/R subframe) and enables the SPDIF transmitter to maintain connection during error or mute conditions. V = 1: Each SPDIF subframe (L+R) has Bit <28> set to 1. This tags both samples as invalid. V = 0: Each SPDIF subframe (L+R) has Bit <28> set to 0 for valid data and 1 for invalid data (error condition). Note that when V = 0, asserting the VFORCE bit (D15) in Register 0x2A (Extended Audio Stat/Ctrl) will force the Validity flag low, marking both samples as valid. |
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