AD5347 datasheet(18/24 Pages) AD

18 / 24 page

AD5346/AD5347/AD5348

Rev. 0 | Page 18 of 24

The bias generator, the output amplifier, the resistor string, and

all other associated linear circuitry are all shut down when the

power-down mode is activated. However, the contents of the

registers are unaffected when in power-down. The time to exit

power-down is typically 2.5 s for VDD = 5 V and 5 µs when VDD =

3 V. This is the time from a rising edge on the PD pin to when

the output voltage deviates from its power-down voltage. See

Figure 31.

SUGGESTED DATA BUS FORMATS

In many applications, the GAIN and BUF pins are hardwired.

However, if more flexibility is required, they can be included in

a data bus. This enables the user to software program GAIN,

giving the option of doubling the resolution in the lower half of

the DAC range. In a bused system, GAIN and BUF may be

treated as data inputs because they are written to the device

during a write operation and take effect when LDAC is taken

low. This means that the reference buffers and the output

amplifier gain of multiple DAC devices can be controlled using

common GAIN and BUF lines. Note that GAIN and BUF are

not read back during an RD operation.

The AD5347 and AD5348 data bus must be at least 10 and 12

bits wide, respectively, and are best suited to a 16-bit data bus

system.

Examples of data formats for putting GAIN and BUF on a

16-bit data bus are shown in Figure 40. Note that any unused

bits above the actual DAC data may be used for GAIN and BUF.

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

GAIN

BUF

X = UNUSED BIT

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

GAIN

BUF

DB11 DB10

AD5347

AD5348

Figure 40. AD5347/AD5348 Data Format for Word Load with

GAIN and BUF Data on 16-Bit Bus

Table 8. AD5346/AD5347/AD5348 Truth Table

CLR

LDAC

Function

No Data Transfer

Clear All Registers

→1

Load DAC A Input Register

→1

Load DAC B Input Register

→1

Load DAC C Input Register

→1

Load DAC D Input Register

→1

Load DAC E Input Register

→1

Load DAC F Input Register

→1

Load DAC G Input Register

→1

Load DAC H Input Register

→0

Read Back DAC Register A

→0

Read Back DAC Register B

→0

Read Back DAC Register C

→0

Read Back DAC Register D

→0

Read Back DAC Register E

→0

Read Back DAC Register F

1→0

Read Back DAC Register G

→0

Read Back DAC Register H

Update DAC Registers

Invalid Operation

X = Don’t Care

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