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AD9860 数据表(PDF) 25 Page - Analog Devices |
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AD9860 数据表(HTML) 25 Page - Analog Devices |
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25 / 32 page  REV. 0 AD9860/AD9862 –25– t R 1 t R 3 t R 2 t R 1 f CLKOUT1 Rx DATA TIMING No. 1 fRx = CLKOUT 4 Rx DATA TIMING No. 2 fRx = CLKOUT 2 Rx DATA TIMING No. 3 fRx = CLKOUT Rx DATA TIMING No. 4 fRx = 2 CLKOUT Figure 9. Rx Timing Diagram 0: B = A 1: B = A/2 00: C = B 01: C = B/2 10: C = B/4 00: E = D 01: E = 2 D 10: E = 4 D ADC SAMPLE RATE (NOT TO EXCEED 64MHz) DLL OUTPUT RATE (NOT TO EXCEED 128MHz) CLKOUT2 INPUT Tx DATA RATE (SINGLE CHANNEL) TxDAC UPDATE RATE SINGLE CHANNEL (CANNOT EXCEED DLL OUTPUT RATE) CLKIN AB D E ADC DIV2 DLL MULT INTERP 00: D = C 01: D = C/2 10: D = C/4 C CLKOUT2 DIV Figure 10. Single Tx Timing Block Diagram, Alternative Operation Table I. Rx Data Timing Table Table Ia. CLKSEL Set Logic Low ADC See Figure 8 for CLKSEL Div 2 Decimate Multiplex Relative Timing Timing No. 4 No Mux Rx Data = 2 CLKOUT1 CLKOUT1 = 1⁄2 CLKIN Mux Not Allowed Timing No. 3 No Mux Rx Data = 2 CLKOUT1 CLKOUT1 = 1⁄2 CLKIN Timing No. 4 Mux Rx Data(MUXED) = 2 CLKOUT1 CLKOUT1 = 1⁄2 CLKIN Timing No. 3 No Mux Rx Data = CLKOUT1 CLKOUT1 = 1⁄2 CLKIN Timing No. 4 Mux Rx Data(MUXED) = 2 CLKOUT1 CLOUT1 = 1⁄2 CLKIN Timing No. 2 No Mux Rx Data = 1⁄2 CLKOUT1 CLOUT1 = 1⁄2 CLKIN Timing No. 3 Mux Rx Data(MUXED) = CLKOUT1 CLKOUT1 = 1⁄2 CLKIN Low Div No Div No Decimation No Decimation Decimation Decimation Table Ib. CLKSEL Set Logic High ADC See Figure 8 for CLKSEL Div 2 Decimate Multiplex Relative Timing Timing No. 3 No Mux Rx Data = CLKOUT1 CLKOUT1 = CLKIN Timing No. 4 Mux Rx Data(MUXED) = 2 CLKOUT1 CLKOUT1 = CLKIN Timing No. 2 No Mux Rx Data = 1⁄2 CLKOUT1 CLKOUT1 = CLKIN Timing No. 3 Mux Rx Data(MUXED) = CLKOUT1 CLKOUT1 = CLKIN Timing No. 2 No Mux Rx Data = 1⁄2 CLKOUT1 CLKOUT1 = CLKIN Timing No. 3 Mux Rx Data(MUXED) = CLKOUT1 CLOUT1 = CLKIN Timing No. 1 No Mux Rx Data = 1⁄4 CLKOUT1 CLOUT1 = CLKIN Timing No. 2 Mux Rx Data(MUXED) = 1⁄2 CLKOUT1 CLKOUT1 = CLKIN High Div No Div No Decimation No Decimation Decimation Decimation |
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